| /external/icu4c/test/cintltst/ |
| D | cbididat.c | 157 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE,
158 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE,
159 AN, RLO, NSM, LRE, PDF, RLE, ES, EN, ON
174 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE,
175 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE,
176 LRE, BN, CS, RLO, S, PDF, EN, LRO, AN, ES
192 L, WS, LRE, WS, R, R, R, WS, PDF, WS, L, L, L, WS, PDF, WS,
268 ON, L, RLO, CS, R, WS, AN, AN, PDF, LRE, R, L, LRO, WS, BN, ON, S, LRE, LRO, B
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| D | cbiditst.h | 46 #define LRE U_LEFT_TO_RIGHT_EMBEDDING macro
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| /external/icu4c/test/testdata/ |
| D | BidiTest.txt | 49 # L LRE R R; 7
50 # L LRE R AL; 7
67 # input lines have the same result (0), since the LRE (item 1) is omitted on the second line.
70 # L LRE; 7
73 @Type: LRE: [\u202A]
93 LRE; 7
142 LRE LRE; 7
143 LRE LRO; 7
144 LRE RLE; 7
145 LRE RLO; 7
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | Spiller.cpp | 183 void spill(LiveRangeEdit &LRE) { in spill() argument
185 trivialSpillEverywhere(&LRE.getParent(), *LRE.getNewVRegs()); in spill()
211 void spill(LiveRangeEdit &LRE) { in spill() argument
213 lis->addIntervalsForSpills(LRE.getParent(), LRE.getUselessVRegs(), in spill()
215 LRE.getNewVRegs()->insert(LRE.getNewVRegs()->end(), in spill()
219 int SS = vrm->getStackSlot(LRE.getReg()); in spill()
222 const TargetRegisterClass *RC = mf->getRegInfo().getRegClass(LRE.getReg()); in spill()
226 SI.MergeRangesInAsValue(LRE.getParent(), SI.getValNumInfo(0)); in spill()
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| D | RegAllocFast.cpp | 162 void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg);
163 void allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint);
470 void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) { in assignVirtToPhysReg() argument
471 DEBUG(dbgs() << "Assigning " << PrintReg(LRE.first, TRI) << " to " in assignVirtToPhysReg()
473 PhysRegState[PhysReg] = LRE.first; in assignVirtToPhysReg()
474 assert(!LRE.second.PhysReg && "Already assigned a physreg"); in assignVirtToPhysReg()
475 LRE.second.PhysReg = PhysReg; in assignVirtToPhysReg()
479 void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) { in allocVirtReg() argument
480 const unsigned VirtReg = LRE.first; in allocVirtReg()
499 return assignVirtToPhysReg(LRE, Hint); in allocVirtReg()
[all …]
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| D | Spiller.h | 29 virtual void spill(LiveRangeEdit &LRE) = 0;
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| D | RegAllocBasic.cpp | 395 LiveRangeEdit LRE(SpilledVReg, SplitVRegs, 0, &PendingSpills); in spillReg() local
396 spiller().spill(LRE); in spillReg()
523 LiveRangeEdit LRE(VirtReg, SplitVRegs); in selectOrSplit() local
524 spiller().spill(LRE); in selectOrSplit()
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| D | RegAllocLinearScan.cpp | 1234 LiveRangeEdit LRE(*cur, added); in assignRegOrStackSlotAtInterval() local
1235 spiller_->spill(LRE); in assignRegOrStackSlotAtInterval()
1311 LiveRangeEdit LRE(*sli, added, 0, &spillIs); in assignRegOrStackSlotAtInterval() local
1312 spiller_->spill(LRE); in assignRegOrStackSlotAtInterval()
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| D | StrongPHIElimination.cpp | 810 for (LiveInterval::iterator LRI = OldLI.begin(), LRE = OldLI.end(); in MergeLIsAndRename() local
811 LRI != LRE; ++LRI) { in MergeLIsAndRename()
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| D | RegAllocGreedy.cpp | 1374 LiveRangeEdit LRE(VirtReg, NewVRegs, this); in selectOrSplit() local
1375 spiller().spill(LRE); in selectOrSplit()
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| /external/icu4c/common/ |
| D | ubidiimp.h | 48 LRE=U_LEFT_TO_RIGHT_EMBEDDING, enumerator
71 #define MASK_LTR (DIRPROP_FLAG(L)|DIRPROP_FLAG(EN)|DIRPROP_FLAG(AN)|DIRPROP_FLAG(LRE)|DIRPROP_FLAG(…
76 #define MASK_LRX (DIRPROP_FLAG(LRE)|DIRPROP_FLAG(LRO))
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| D | ubidi.c | 109 static const Flags flagE[2]={ DIRPROP_FLAG(LRE), DIRPROP_FLAG(RLE) };
626 case LRE: in resolveExplicitLevels()
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| /external/webkit/Source/WebKit/gtk/po/ |
| D | gr.po | 37 msgid "LRE Left-to-right _embedding"
38 msgstr "LRE _Ενσωμάτωση αριστερά προς δεξιά"
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| D | et.po | 35 msgid "LRE Left-to-right _embedding"
36 msgstr "LRE Va_sakult paremale põimimine"
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| D | lv.po | 37 msgid "LRE Left-to-right _embedding"
38 msgstr "LRE No kreisās uz labo _iegultīšana"
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| D | uk.po | 37 msgid "LRE Left-to-right _embedding"
38 msgstr "LRE вс_тавка зліва направо"
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| D | zh_CN.po | 37 msgid "LRE Left-to-right _embedding"
38 msgstr "LRE 左至右嵌入(_E)"
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| D | gu.po | 40 msgid "LRE Left-to-right _embedding"
41 msgstr "LRE Left-to-right _embedding"
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| D | ru.po | 36 msgid "LRE Left-to-right _embedding"
37 msgstr "LRE Вс_тавка слева направо"
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| D | pa.po | 36 msgid "LRE Left-to-right _embedding"
37 msgstr "LRE ਖੱਬੇ ਤੋਂ ਸੱਜੇ ਇੰਬੈੱਡ(_e)"
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| D | bg.po | 37 msgid "LRE Left-to-right _embedding"
38 msgstr "_Вмъкване отляво-надясно — LRE"
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| D | ar.po | 37 msgid "LRE Left-to-right _embedding"
38 msgstr "_غرس يسار إلى يمين (LRE)"
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| D | he.po | 37 msgid "LRE Left-to-right _embedding"
38 msgstr "LRE _שיבוץ משמאל לימין"
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| D | ko.po | 38 msgid "LRE Left-to-right _embedding"
39 msgstr "LRE 왼쪽에서-오른쪽으로 임베딩(_E)"
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| D | en_GB.po | 36 msgid "LRE Left-to-right _embedding"
37 msgstr "LRE Left-to-right _embedding"
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