| /external/llvm/lib/CodeGen/ |
| D | AllocationOrder.cpp | 44 ArrayRef<unsigned> Order = in AllocationOrder() local
47 if (Order.empty()) in AllocationOrder()
52 unsigned *P = new unsigned[Order.size()]; in AllocationOrder()
54 for (unsigned i = 0; i != Order.size(); ++i) in AllocationOrder()
55 if (!RCI.isReserved(Order[i])) in AllocationOrder()
56 *P++ = Order[i]; in AllocationOrder()
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| D | RegisterClassInfo.cpp | 76 if (!RCI.Order) in compute()
77 RCI.Order.reset(new unsigned[NumRegs]); in compute()
94 RCI.Order[N++] = PhysReg; in compute()
100 std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]); in compute()
105 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI); in compute()
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| D | ScheduleDAGInstrs.cpp | 373 ExitSU.addPred(SDep(SU, SDep::Order, Latency, in BuildSchedGraph()
428 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0)); in BuildSchedGraph()
433 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency)); in BuildSchedGraph()
439 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0)); in BuildSchedGraph()
446 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0)); in BuildSchedGraph()
449 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency)); in BuildSchedGraph()
452 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0)); in BuildSchedGraph()
457 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency)); in BuildSchedGraph()
474 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0, in BuildSchedGraph()
490 J->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency, in BuildSchedGraph()
[all …]
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| D | RegAllocGreedy.cpp | 388 AllocationOrder &Order, in tryAssign() argument
390 Order.rewind(); in tryAssign()
392 while ((PhysReg = Order.next())) in tryAssign()
395 if (!PhysReg || Order.isHint(PhysReg)) in tryAssign()
403 if (Order.isHint(Hint)) { in tryAssign()
421 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost); in tryAssign()
557 AllocationOrder &Order, in tryEvict() argument
573 Order.rewind(); in tryEvict()
574 while (unsigned PhysReg = Order.next()) { in tryEvict()
594 if (Order.isHint(PhysReg)) in tryEvict()
[all …]
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| D | RegisterClassInfo.h | 31 OwningArrayPtr<unsigned> Order; member
35 return makeArrayRef(Order.get(), NumRegs);
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| D | RegAllocLinearScan.cpp | 1160 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC); in assignRegOrStackSlotAtInterval() local
1162 for (unsigned i = 0; i != Order.size(); ++i) { in assignRegOrStackSlotAtInterval()
1163 unsigned reg = Order[i]; in assignRegOrStackSlotAtInterval()
1173 for (unsigned i = 0; i != Order.size(); ++i) { in assignRegOrStackSlotAtInterval()
1174 unsigned reg = Order[i]; in assignRegOrStackSlotAtInterval()
1434 ArrayRef<unsigned> Order; in getFreePhysReg() local
1436 Order = tri_->getRawAllocationOrder(RC, Hint.first, physReg, *mf_); in getFreePhysReg()
1438 Order = RegClassInfo.getOrder(RC); in getFreePhysReg()
1440 assert(!Order.empty() && "No allocatable register in this register class!"); in getFreePhysReg()
1443 for (unsigned i = 0; i != Order.size(); ++i) { in getFreePhysReg()
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| D | AggressiveAntiDepBreaker.cpp | 623 ArrayRef<unsigned> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters() local
624 if (Order.empty()) { in FindSuitableFreeRegisters()
632 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
635 unsigned EndR = ((OrigR == Order.size()) ? 0 : OrigR); in FindSuitableFreeRegisters()
638 if (R == 0) R = Order.size(); in FindSuitableFreeRegisters()
640 const unsigned NewSuperReg = Order[R]; in FindSuitableFreeRegisters()
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| D | RegAllocBasic.cpp | 485 ArrayRef<unsigned> Order = in selectOrSplit() local
487 for (ArrayRef<unsigned>::iterator I = Order.begin(), E = Order.end(); I != E; in selectOrSplit()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 51 Order ///< Any other ordering dependency. enumerator
80 } Order; member
110 case Order: in Dep()
112 Contents.Order.isNormalMemory = isNormalMemory; in Dep()
113 Contents.Order.isMustAlias = isMustAlias; in Dep()
114 Contents.Order.isArtificial = isArtificial; in Dep()
126 case Order:
127 return Contents.Order.isNormalMemory ==
128 Other.Contents.Order.isNormalMemory &&
129 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias &&
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SDNodeDbgValue.h | 50 unsigned Order; variable
55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O), in SDDbgValue()
65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) { in SDDbgValue()
72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) { in SDDbgValue()
103 unsigned getOrder() { return Order; } in getOrder()
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| D | ScheduleDAGSDNodes.cpp | 448 const SDep &dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data, in AddSchedEdges()
638 unsigned Order) { in ProcessSDDbgValues() argument
651 if (!Order || DVOrder == ++Order) { in ProcessSDDbgValues()
670 unsigned Order = DAG->GetOrdering(N); in ProcessSourceNode() local
671 if (!Order || !Seen.insert(Order)) { in ProcessSourceNode()
681 Orders.push_back(std::make_pair(Order, (MachineInstr*)0)); in ProcessSourceNode()
685 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos()))); in ProcessSourceNode()
686 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
761 unsigned Order = Orders[i].first; in EmitSchedule() local
767 (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) { in EmitSchedule()
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| /external/icu4c/test/intltest/ |
| D | tscoll.cpp | 404 LocalArray<Order> orders(getOrders(iter, orderLength)); in backAndForth()
497 IntlTestCollator::Order *IntlTestCollator::getOrders(CollationElementIterator &iter, int32_t &order… in getOrders()
501 LocalArray<Order> orders(new Order[maxSize]); in getOrders()
511 Order *temp = new Order[maxSize]; in getOrders()
513 uprv_memcpy(temp, orders.getAlias(), size * sizeof(Order)); in getOrders()
526 Order *temp = new Order[size]; in getOrders()
528 uprv_memcpy(temp, orders.getAlias(), size * sizeof(Order)); in getOrders()
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| D | tscoll.h | 26 struct Order struct
51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength); argument
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| D | ssearch.cpp | 674 struct Order struct
690 const Order *get(int32_t index) const; argument
699 Order *list;
707 list = new Order[listMax]; in OrderList()
732 list = new Order[listMax]; in OrderList()
763 Order *newList = new Order[listMax]; in add()
765 uprv_memcpy(newList, list, listSize * sizeof(Order)); in add()
777 const Order *OrderList::get(int32_t index) const in get()
788 const Order *order = get(index); in getLowOffset()
799 const Order *order = get(index); in getHighOffset()
[all …]
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| /external/llvm/lib/Target/ |
| D | TargetRegisterInfo.cpp | 76 ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF); in getAllocatableSetForRC() local
77 for (unsigned i = 0; i != Order.size(); ++i) in getAllocatableSetForRC()
78 R.set(Order[i]); in getAllocatableSetForRC()
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| /external/webkit/LayoutTests/http/conf/ |
| D | apache2-httpd.conf | 316 Order allow,deny
338 Order allow,deny
348 Order allow,deny
354 Order allow,deny
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| D | apache2-msys-httpd.conf | 317 Order allow,deny
339 Order allow,deny
349 Order allow,deny
355 Order allow,deny
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| D | fedora-httpd.conf | 336 Order allow,deny
381 Order allow,deny
391 Order allow,deny
397 Order allow,deny
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| D | apache2-debian-httpd.conf | 295 Order allow,deny
317 Order allow,deny
327 Order allow,deny
333 Order allow,deny
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| D | httpd.conf | 351 Order allow,deny
373 Order allow,deny
383 Order allow,deny
389 Order allow,deny
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| D | cygwin-httpd.conf | 348 Order allow,deny
370 Order allow,deny
380 Order allow,deny
386 Order allow,deny
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| /external/zlib/qnx/ |
| D | package.qpg | 117 <QPM:Order>InstallOver</QPM:Order>
131 <QPM:Order>InstallOver</QPM:Order>
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 283 SetTheory::RecSet Order; in CodeGenRegisterClass() local
285 RegBank.getSets().evaluate(Alts->getElement(i), Order); in CodeGenRegisterClass()
286 AltOrders[i].append(Order.begin(), Order.end()); in CodeGenRegisterClass()
288 while (!Order.empty()) { in CodeGenRegisterClass()
289 CodeGenRegister *Reg = RegBank.getReg(Order.back()); in CodeGenRegisterClass()
290 Order.pop_back(); in CodeGenRegisterClass()
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| D | RegisterInfoEmitter.cpp | 414 ArrayRef<Record*> Order = RC.getOrder(); in runTargetDesc() local
418 AllocatableRegs.insert(Order.begin(), Order.end()); in runTargetDesc()
427 for (unsigned i = 0, e = Order.size(); i != e; ++i) { in runTargetDesc()
428 Record *Reg = Order[i]; in runTargetDesc()
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| /external/icu4c/data/lang/ |
| D | en.txt | 723 big5han{"Traditional Chinese Sort Order - Big5"}
724 direct{"Direct Sort Order"}
725 gb2312han{"Simplified Chinese Sort Order - GB2312"}
726 phonebook{"Phonebook Sort Order"}
727 pinyin{"Simplified Chinese Pinyin Sort Order"}
729 stroke{"Traditional Chinese Stroke Sort Order"}
730 traditional{"Traditional Sort Order"}
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