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Searched refs:Pat (Results 1 – 25 of 45) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86InstrCompiler.td11 // as well as Pat patterns used during instruction selection.
179 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
180 // However, Pat<> can't replicate the destination reg into the inputs of the
196 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
198 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
200 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
203 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
205 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
207 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
214 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
[all …]
DX86InstrSSE.td166 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
170 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
176 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
179 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
182 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
185 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
191 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
193 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
195 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
199 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
[all …]
DX86InstrFPStack.td604 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
605 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
606 def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>;
609 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
610 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op,
612 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
613 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op,
615 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op,
617 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op,
621 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>;
[all …]
DX86InstrMMX.td414 def : Pat<(v2i64 (MMX_X86movq2dq VR64:$src)),
417 def : Pat<(v2i64 (MMX_X86movq2dq (load_mmx addr:$src))),
420 def : Pat<(v2i64 (MMX_X86movq2dq
428 def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)),
431 def : Pat<(x86mmx (MMX_X86movdq2q (loadv2i64 addr:$src))),
445 def : Pat<(x86mmx (bitconvert (i64 GR64:$src))),
447 def : Pat<(i64 (bitconvert (x86mmx VR64:$src))),
449 def : Pat<(f64 (bitconvert (x86mmx VR64:$src))),
451 def : Pat<(x86mmx (bitconvert (f64 FR64:$src))),
/external/llvm/lib/Target/CellSPU/
DSPU128InstrInfo.td8 def : Pat<(i128 (zext R32C:$rSrc)),
12 def : Pat<(i128 (zext R64C:$rSrc)),
16 def : Pat<(i128 (zext R16C:$rSrc)),
20 def : Pat<(i128 (zext R8C:$rSrc)),
24 def : Pat<(i128 (anyext R32C:$rSrc)),
28 def : Pat<(i128 (anyext R64C:$rSrc)),
32 def : Pat<(i128 (anyext R16C:$rSrc)),
36 def : Pat<(i128 (anyext R8C:$rSrc)),
40 def : Pat<(shl GPRC:$rA, R32C:$rB),
DSPUInstrInfo.td427 // into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...>
562 def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
1427 def : Pat<(v16i8 (SPUprefslot2vec R8C:$rA)),
1430 def : Pat<(v8i16 (SPUprefslot2vec R16C:$rA)),
1433 def : Pat<(v4i32 (SPUprefslot2vec R32C:$rA)),
1436 def : Pat<(v2i64 (SPUprefslot2vec R64C:$rA)),
1439 def : Pat<(v4f32 (SPUprefslot2vec R32FP:$rA)),
1442 def : Pat<(v2f64 (SPUprefslot2vec R64FP:$rA)),
1445 def : Pat<(i8 (SPUvec2prefslot (v16i8 VECREG:$rA))),
1448 def : Pat<(i16 (SPUvec2prefslot (v8i16 VECREG:$rA))),
[all …]
DSPU64InstrInfo.td40 def : Pat<(select R32C:$rCond, R64C:$rFalse, R64C:$rTrue),
45 Pat<(select (i32 (cond R64C:$rA, R64C:$rB)), R64C:$rTrue, R64C:$rFalse),
50 Pat<(cond R64C:$rA, R64C:$rB),
82 def : Pat<(seteq R64C:$rA, R64C:$rB), I64EQr64.Fragment>;
83 def : Pat<(seteq (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)), I64EQv2i64.Fragment>;
131 def : Pat<(setugt R64C:$rA, R64C:$rB), I64LGTr64.Fragment>;
132 //def : Pat<(setugt (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)),
165 def : Pat<(setuge R64C:$rA, R64C:$rB), I64LGEr64.Fragment>;
166 def : Pat<(v2i64 (setuge (v2i64 VECREG:$rA), (v2i64 VECREG:$rB))),
216 def : Pat<(setgt R64C:$rA, R64C:$rB), I64GTr64.Fragment>;
[all …]
DSPUMathInstr.td17 def : Pat<(mul (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)),
36 def : Pat<(mul (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
46 Pat<(mul (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)),
53 Pat<(mul R32C:$rA, R32C:$rB),
74 def : Pat<(fdiv R32FP:$rA, R32FP:$rB),
92 def : Pat<(fdiv (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
/external/llvm/lib/Target/Alpha/
DAlphaInstrInfo.td209 def : Pat<(select GPRC:$which, GPRC:$src1, GPRC:$src2),
211 def : Pat<(select GPRC:$which, GPRC:$src1, immUExt8:$src2),
215 def : Pat<(select (setne GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
217 def : Pat<(select (setgt GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
219 def : Pat<(select (setge GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
221 def : Pat<(select (setlt GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
223 def : Pat<(select (setle GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
246 def : Pat<(intop (add GPRC:$RA, immUExt8neg:$L)), (SUBLi GPRC:$RA, immUExt8neg:$L)>;
247 def : Pat<(add GPRC:$RA, immUExt8neg:$L), (SUBQi GPRC:$RA, immUExt8neg:$L)>;
248 def : Pat<(intop (add4 GPRC:$RA, immUExt8neg:$L)), (S4SUBLi GPRC:$RA, immUExt8neg:$L)>;
[all …]
/external/llvm/lib/Target/MBlaze/
DMBlazeInstrFPU.td133 def : Pat<(sint_to_fp GPR:$V), (FLT GPR:$V)>;
134 def : Pat<(fp_to_sint GPR:$V), (FINT GPR:$V)>;
135 def : Pat<(fsqrt GPR:$V), (FSQRT GPR:$V)>;
140 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETEQ),
143 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETNE),
146 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOEQ),
149 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
153 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
157 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGT),
160 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLT),
[all …]
DMBlazeInstrInfo.td725 def : Pat<(i32 0), (ADDK (i32 R0), (i32 R0))>;
726 def : Pat<(i32 immSExt16:$imm), (ADDIK (i32 R0), imm:$imm)>;
727 def : Pat<(i32 immZExt16:$imm), (ORI (i32 R0), imm:$imm)>;
730 def : Pat<(i32 imm:$imm), (ADDIK (i32 R0), imm:$imm)>;
733 def : Pat<(sext_inreg GPR:$src, i16), (SEXT16 GPR:$src)>;
734 def : Pat<(sext_inreg GPR:$src, i8), (SEXT8 GPR:$src)>;
737 def : Pat<(MBlazeJmpLink (i32 tglobaladdr:$dst)),
740 def : Pat<(MBlazeJmpLink (i32 texternalsym:$dst)),
743 def : Pat<(MBlazeJmpLink GPR:$dst),
747 def : Pat<(shl GPR:$L, GPR:$R), (ShiftL GPR:$L, GPR:$R)>;
[all …]
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.td1033 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>;
1034 def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;
1037 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
1038 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
1039 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
1042 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1044 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1046 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1048 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1050 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
[all …]
/external/llvm/lib/Target/Mips/
DMipsInstrInfo.td661 def : Pat<(i32 immSExt16:$in),
663 def : Pat<(i32 immZExt16:$in),
667 def : Pat<(i32 imm:$imm),
671 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
673 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
675 def : Pat<(addc CPURegs:$src, immSExt16:$imm),
679 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
681 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
683 //def : Pat<(MipsJmpLink CPURegs:$dst),
687 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
[all …]
DMipsInstrFPU.td355 def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
356 def : Pat<(f32 fpimm0neg), (FNEG_S32 (MTC1 ZERO))>;
358 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVTS_W32 (MTC1 CPURegs:$src))>;
359 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>;
361 def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S32 FGR32:$src))>;
362 def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
364 def : Pat<(i32 (bitconvert FGR32:$src)), (MFC1 FGR32:$src)>;
365 def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1 CPURegs:$src)>;
368 def : Pat<(f32 (fround AFGR64:$src)), (CVTS_D32 AFGR64:$src)>;
369 def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S32 FGR32:$src)>;
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td577 def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>;
578 def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>;
581 def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM),
583 def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM),
585 def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM),
587 def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM),
591 def : Pat<(int_ppc_altivec_dst G8RC:$rA, GPRC:$rB, imm:$STRM),
593 def : Pat<(int_ppc_altivec_dstt G8RC:$rA, GPRC:$rB, imm:$STRM),
595 def : Pat<(int_ppc_altivec_dstst G8RC:$rA, GPRC:$rB, imm:$STRM),
597 def : Pat<(int_ppc_altivec_dststt G8RC:$rA, GPRC:$rB, imm:$STRM),
[all …]
DPPCInstr64Bit.td78 "bl $func", BrB, []>; // See Pat patterns below.
104 … "bl $func", BrB, []>; // See Pat patterns below.
119 def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)),
121 def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)),
124 def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)),
126 def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)),
128 def : Pat<(PPCnop),
217 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
220 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
223 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
[all …]
DPPCInstrInfo.td445 "bl $func", BrB, []>; // See Pat patterns below.
470 "bl $func", BrB, []>; // See Pat patterns below.
1349 def : Pat<(i32 imm:$imm),
1353 def NOT : Pat<(not GPRC:$in),
1357 def : Pat<(add GPRC:$in, imm:$imm),
1360 def : Pat<(or GPRC:$in, imm:$imm),
1363 def : Pat<(xor GPRC:$in, imm:$imm),
1366 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1370 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1372 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
[all …]
/external/llvm/lib/Target/Blackfin/
DBlackfinInstrInfo.td216 def : Pat<(BfinWrapper (i32 tglobaladdr:$addr)),
219 def : Pat<(BfinWrapper (i32 tjumptable:$addr)),
262 def : Pat<(i32 (extloadi16 P:$ptr)),(LOAD32p_16z P:$ptr)>;
269 def : Pat<(i32 (extloadi16 (add P:$ptr, uimm5m2:$off))),
277 def : Pat<(i32 (extloadi16 (add P:$ptr, imm17m2:$off))),
302 def : Pat<(i32 (extloadi8 P:$ptr)), (LOAD32p_8z P:$ptr)>;
303 def : Pat<(i16 (extloadi8 P:$ptr)),
305 def : Pat<(i16 (zextloadi8 P:$ptr)),
312 def : Pat<(i32 (extloadi8 (add P:$ptr, imm16:$off))),
314 def : Pat<(i16 (extloadi8 (add P:$ptr, imm16:$off))),
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td305 def : Pat<(i16 (zext def8:$src)),
1127 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1130 def : Pat<(i16 (anyext GR8:$src)),
1134 def : Pat<(i8 (trunc GR16:$src)),
1138 def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>;
1139 def : Pat<(i16 (MSP430Wrapper texternalsym:$dst)), (MOV16ri texternalsym:$dst)>;
1140 def : Pat<(i16 (MSP430Wrapper tblockaddress:$dst)), (MOV16ri tblockaddress:$dst)>;
1142 def : Pat<(add GR16:$src, (MSP430Wrapper tglobaladdr :$src2)),
1144 def : Pat<(add GR16:$src, (MSP430Wrapper texternalsym:$src2)),
1146 def : Pat<(add GR16:$src, (MSP430Wrapper tblockaddress:$src2)),
[all …]
/external/llvm/utils/TableGen/
DCodeGenDAGPatterns.cpp1711 TreePattern::TreePattern(Record *TheRec, DagInit *Pat, bool isInput, in TreePattern() argument
1714 Trees.push_back(ParseTreePattern(Pat, "")); in TreePattern()
1717 TreePattern::TreePattern(Record *TheRec, TreePatternNode *Pat, bool isInput, in TreePattern() argument
1720 Trees.push_back(Pat); in TreePattern()
2229 static bool HandleUse(TreePattern *I, TreePatternNode *Pat, in HandleUse() argument
2232 if (Pat->getName().empty()) { in HandleUse()
2233 if (Pat->isLeaf()) { in HandleUse()
2234 DefInit *DI = dynamic_cast<DefInit*>(Pat->getLeafValue()); in HandleUse()
2243 if (Pat->isLeaf()) { in HandleUse()
2244 DefInit *DI = dynamic_cast<DefInit*>(Pat->getLeafValue()); in HandleUse()
[all …]
DCodeGenRegisters.cpp96 DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i)); in getSubRegs() local
97 if (!Pat) in getSubRegs()
101 DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator()); in getSubRegs()
104 Pat->getAsString()); in getSubRegs()
108 for (DagInit::const_arg_iterator di = Pat->arg_begin(), in getSubRegs()
109 de = Pat->arg_end(); di != de; ++di) { in getSubRegs()
113 Pat->getAsString()); in getSubRegs()
117 throw TGError(TheDef->getLoc(), "Composite " + Pat->getAsString() + in getSubRegs()
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td568 def : Pat<(vector_insert (v2f32 DPR:$src),
571 def : Pat<(vector_insert (v4f32 QPR:$src),
842 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
844 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1418 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1420 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
3332 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3338 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3344 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3358 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.td777 def : Pat<(ctpop IntRegs:$src),
785 def : Pat<(i32 simm13:$val),
788 def : Pat<(i32 imm:$val),
792 def : Pat<(subc IntRegs:$b, IntRegs:$c),
794 def : Pat<(subc IntRegs:$b, simm13:$val),
798 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
799 def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
800 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
801 def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>;
804 def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)),
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.td1087 def : Pat<(SystemZpcrelwrapper tjumptable:$src), (LA64rm tjumptable:$src)>;
1088 def : Pat<(SystemZpcrelwrapper tconstpool:$src), (LA64rm tconstpool:$src)>;
1091 def : Pat<(i64 (anyext GR32:$src)),
1095 def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), (CALLi tglobaladdr:$dst)>;
1096 def : Pat<(SystemZcall (i64 texternalsym:$dst)), (CALLi texternalsym:$dst)>;
1105 def : Pat<(i32 imm:$src),
1110 def : Pat<(i64 imm:$imm),
1114 def : Pat<(i32 (trunc GR64:$src)),
1118 def : Pat<(sext_inreg GR64:$src, i32),
1122 def : Pat<(extloadi32i8 rriaddr:$src), (MOVZX32rm8 rriaddr:$src)>;
[all …]
/external/llvm/utils/FileCheck/
DFileCheck.cpp439 Pattern Pat; member
454 : Pat(P), Loc(L), IsCheckNext(isCheckNext) {} in CheckString()
621 CheckStr.Pat.PrintFailureInfo(SM, Buffer, VariableTable); in PrintCheckFailed()
693 size_t MatchPos = CheckStr.Pat.Match(Buffer, MatchLen, VariableTable); in main()

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