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Searched refs:TB (Results 1 – 25 of 52) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86InstrSystem.td17 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB;
20 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
25 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
26 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
30 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
47 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
48 def SYSRETL : I<0x07, RawFrm, (outs), (ins), "sysretl", []>, TB;
49 def SYSRETQ :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
52 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
54 def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit", []>, TB,
[all …]
DX86InstrVMX.td23 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
25 "vmclear\t$vmcs", []>, OpSize, TB;
27 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
29 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
31 "vmptrld\t$vmcs", []>, TB;
33 "vmptrst\t$vmcs", []>, TB;
35 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
37 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
39 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
41 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
[all …]
DX86InstrExtension.td42 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
44 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
47 [(set GR32:$dst, (sext GR8:$src))]>, TB;
50 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
53 [(set GR32:$dst, (sext GR16:$src))]>, TB;
56 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
59 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
61 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
64 [(set GR32:$dst, (zext GR8:$src))]>, TB;
67 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
[all …]
DX86InstrCMovSetCC.td24 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>,TB,OpSize;
29 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))]>, TB;
34 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))]>, TB;
42 CondNode, EFLAGS))]>, TB, OpSize;
47 CondNode, EFLAGS))]>, TB;
52 CondNode, EFLAGS))]>, TB;
81 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))]>, TB;
84 [(store (X86setcc OpNode, EFLAGS), addr:$dst)]>, TB;
DX86InstrInfo.td604 "nop{w}\t$zero", []>, TB, OpSize;
606 "nop{l}\t$zero", []>, TB;
716 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
720 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
727 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
730 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
734 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
737 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
740 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
743 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
[all …]
DX86InstrFormats.td94 class TB { bits<5> Prefix = 1; }
301 // PSI - SSE1 instructions with TB prefix.
302 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
304 // VPSI - SSE1 instructions with TB prefix in AVX form.
312 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
316 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
324 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>, TB,
332 // PDI - SSE2 instructions with TB and OpSize prefixes.
333 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
335 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
[all …]
DX86InstrShiftRotate.td605 TB, OpSize;
610 TB, OpSize;
614 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
618 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
623 TB;
628 TB;
638 TB, OpSize;
645 TB, OpSize;
652 TB;
659 TB;
[all …]
DX86InstrMMX.td360 SSEPackedSingle>, TB;
363 SSEPackedDouble>, TB, OpSize;
366 SSEPackedSingle>, TB;
369 SSEPackedDouble>, TB, OpSize;
372 SSEPackedDouble>, TB, OpSize;
377 SSEPackedSingle>, TB;
DX86InstrSSE.td268 "movaps", SSEPackedSingle>, TB;
270 "movapd", SSEPackedDouble>, TB, OpSize;
272 "movups", SSEPackedSingle>, TB;
274 "movupd", SSEPackedDouble, 0>, TB, OpSize;
349 SSEPackedSingle>, TB;
356 SSEPackedDouble>, TB, OpSize;
669 SSEPackedSingle>, TB, VEX;
672 SSEPackedSingle>, TB, VEX;
681 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
778 TB, VEX, Requires<[HasAVX]>;
[all …]
DX86Instr3DNow.td16 : I<o, F, outs, ins, asm, pat>, TB, Requires<[Has3DNow]> {
DX86InstrCompiler.td672 [(X86cas8 addr:$ptr)]>, TB, LOCK;
678 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
685 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
692 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
699 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
708 TB, LOCK;
713 TB, OpSize, LOCK;
718 TB, LOCK;
723 TB, LOCK;
DX86InstrInfo.h357 TB = 1 << Op0Shift, enumerator
DX86MCCodeEmitter.cpp475 case X86II::TB: // Bypass: Not used by VEX in EmitVEXOpcodePrefix()
744 case X86II::TB: // Two-byte opcode prefix in EmitOpcodePrefix()
/external/clang/test/CXX/special/class.dtor/
Dp3-0x.cpp66 struct TB { struct
67 ~TB() throw(int);
72 TB<T> b;
114 TB<T> b;
/external/qemu/docs/
DCPU-EMULATION.TXT11 Each fragment is translated into a "translated block" (a.k.a. TB) of host
13 instruction pointer changes (i.e. at the end of TB execution), a hash
14 table lookup is performed to find the next TB to execute.
17 sometimes possible to 'link' the end of a given TB to the start of
21 (described below in "MMU emulation"), there are actually two TB caches per
33 into a TB. This is done by decomposing each instruction into a series of
/external/llvm/test/CodeGen/X86/
Disel-sink2.ll10 br i1 %T, label %TB, label %F
11 TB:
/external/clang/test/SemaCXX/
Dvirtual-override.cpp224 template <int N> struct TB {}; struct
225 struct D : public TB<0> {};
229 virtual TB<N>* f2(); // expected-note{{overridden virtual function is here}}
/external/llvm/lib/Target/Alpha/
DAlphaInstrFormats.td74 class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, InstrItinClass itin>
85 let Inst{15-14} = TB;
88 class MbrpForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, list<dag> pattern, InstrItinClass…
100 let Inst{15-14} = TB;
/external/llvm/lib/Target/MBlaze/
DMBlazeInstrInfo.td171 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
176 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
205 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
230 TB<op, (outs GPR:$dst), (ins GPR:$b, uimm16:$c),
236 TB<op, (outs GPR:$dst), (ins GPR:$b, uimm16:$c),
257 TB<op, (outs GPR:$dst), (ins memri:$addr),
269 TB<op, (outs), (ins GPR:$dst, memri:$addr),
286 TB<op, (outs), (ins brtarget:$target),
306 TB<op, (outs), (ins GPR:$link, calltarget:$target, variable_ops),
326 TB<op, (outs), (ins GPR:$a, brtarget:$offset),
[all …]
DMBlazeInstrFPU.td27 TB<op, (outs GPR:$dst), (ins memri:$addr),
37 TB<op, (outs), (ins GPR:$dst, memrr:$addr),
60 TB<op, (outs GPR:$dst), (ins GPR:$b, fimm:$c),
DMBlazeInstrFormats.td108 class TB<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
147 TB<op, outs, ins, asmstr, pattern, itin> {
/external/qemu/tcg/
DTODO9 - Move the slow part of the qemu_ld/st ops after the end of the TB.
DREADME17 A TCG "function" corresponds to a QEMU Translated Block (TB).
383 Exit the current TB and return the value t0 (word type).
387 Exit the current TB and jump to the TB index 'index' (constant) if the
388 current TB was linked to this TB. Otherwise execute the next
/external/qemu/target-i386/
DTODO31 - find a way to avoid translating several time the same TB if CR0.TS
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp65 TB = 1, enumerator
765 case X86Local::TB: in emitDecodePath()

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