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Searched refs:DefMI (Results 1 – 23 of 23) sorted by relevance

/external/llvm/lib/CodeGen/
DLiveRangeEdit.cpp46 const MachineInstr *DefMI, in checkRematerializable() argument
48 assert(DefMI && "Missing instruction"); in checkRematerializable()
50 if (!TII.isTriviallyReMaterializable(DefMI, aa)) in checkRematerializable()
62 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def); in scanRemattable() local
63 if (!DefMI) in scanRemattable()
65 checkRematerializable(VNI, DefMI, aa); in scanRemattable()
151 MachineInstr *DefMI = 0, *UseMI = 0; in foldAsLoad() local
159 if (DefMI && DefMI != MI) in foldAsLoad()
163 DefMI = MI; in foldAsLoad()
173 if (!DefMI || !UseMI) in foldAsLoad()
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DTwoAddressInstructionPass.cpp96 MachineInstr *MI, MachineInstr *DefMI,
324 MachineInstr *MI, MachineInstr *DefMI, in isProfitableToReMat() argument
350 return MBB == DefMI->getParent(); in isProfitableToReMat()
445 MachineInstr *DefMI = &MI; in isKilled() local
447 if (!DefMI->killsRegister(Reg)) in isKilled()
456 DefMI = &*Begin; in isKilled()
461 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) in isKilled()
1038 MachineInstr *DefMI = &*DI; in isDefTooClose() local
1039 if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike()) in isDefTooClose()
1041 if (DefMI == MI) in isDefTooClose()
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DPHIElimination.cpp138 MachineInstr *DefMI = *I; in runOnMachineFunction() local
139 unsigned DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction()
141 DefMI->eraseFromParent(); in runOnMachineFunction()
180 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in isSourceDefinedByImplicitDef() local
181 if (!DefMI || !DefMI->isImplicitDef()) in isSourceDefinedByImplicitDef()
300 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in LowerAtomicPHINode() local
301 if (DefMI->isImplicitDef()) { in LowerAtomicPHINode()
302 ImpDefs.insert(DefMI); in LowerAtomicPHINode()
DInlineSpiller.cpp109 MachineInstr *DefMI; member
120 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {} in SibValueInfo()
123 bool hasDef() const { return DefByOrigPHI || DefMI; } in hasDef()
331 if (SVI.DefMI) in operator <<()
332 OS << " def: " << *SVI.DefMI; in operator <<()
395 DepSV.DefMI = SV.DefMI; in propagateSiblingValue()
484 return SVI->second.DefMI; in traceSiblingValue()
602 SVI->second.DefMI = MI; in traceSiblingValue()
623 return SVI->second.DefMI; in traceSiblingValue()
646 MachineInstr *DefMI = 0; in analyzeSiblingValues() local
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DRegisterCoalescer.cpp170 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
621 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); in RemoveCopyByCommutingDef() local
622 if (!DefMI) in RemoveCopyByCommutingDef()
624 if (!DefMI->isCommutable()) in RemoveCopyByCommutingDef()
628 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); in RemoveCopyByCommutingDef()
631 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) in RemoveCopyByCommutingDef()
634 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) in RemoveCopyByCommutingDef()
643 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); in RemoveCopyByCommutingDef()
676 << *DefMI); in RemoveCopyByCommutingDef()
680 MachineBasicBlock *MBB = DefMI->getParent(); in RemoveCopyByCommutingDef()
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DPeepholeOptimizer.cpp295 MachineInstr *DefMI = MRI->getVRegDef(Src); in OptimizeBitcastInstr() local
296 if (!DefMI || !DefMI->isBitcast()) in OptimizeBitcastInstr()
300 NumDefs = DefMI->getDesc().getNumDefs(); in OptimizeBitcastInstr()
301 NumSrcs = DefMI->getDesc().getNumOperands() - NumDefs; in OptimizeBitcastInstr()
305 const MachineOperand &MO = DefMI->getOperand(i); in OptimizeBitcastInstr()
DMachineCSE.cpp132 MachineInstr *DefMI = MRI->getVRegDef(Reg); in INITIALIZE_PASS_DEPENDENCY() local
133 if (DefMI->getParent() != MBB) in INITIALIZE_PASS_DEPENDENCY()
135 if (!DefMI->isCopy()) in INITIALIZE_PASS_DEPENDENCY()
137 unsigned SrcReg = DefMI->getOperand(1).getReg(); in INITIALIZE_PASS_DEPENDENCY()
140 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg()) in INITIALIZE_PASS_DEPENDENCY()
144 DEBUG(dbgs() << "Coalescing: " << *DefMI); in INITIALIZE_PASS_DEPENDENCY()
148 DefMI->eraseFromParent(); in INITIALIZE_PASS_DEPENDENCY()
DScheduleDAGInstrs.cpp764 MachineInstr *DefMI = Def->getInstr(); in computeOperandLatency() local
765 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg); in computeOperandLatency()
767 const MachineOperand &MO = DefMI->getOperand(DefIdx); in computeOperandLatency()
769 DefIdx >= (int)DefMI->getDesc().getNumOperands()) { in computeOperandLatency()
776 unsigned Op2 = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI); in computeOperandLatency()
777 if (DefMI->getOperand(Op2).isReg()) in computeOperandLatency()
792 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx, in computeOperandLatency()
800 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
DMachineSink.cpp131 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in INITIALIZE_PASS_DEPENDENCY() local
132 if (DefMI->isCopyLike()) in INITIALIZE_PASS_DEPENDENCY()
134 DEBUG(dbgs() << "Coalescing: " << *DefMI); in INITIALIZE_PASS_DEPENDENCY()
DStrongPHIElimination.cpp253 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in runOnMachineFunction() local
254 if (DefMI) in runOnMachineFunction()
255 PHISrcDefs[DefMI->getParent()].push_back(DefMI); in runOnMachineFunction()
DTailDuplication.cpp227 MachineInstr *DefMI = MRI->getVRegDef(VReg); in TailDuplicateAndUpdate() local
229 if (DefMI) { in TailDuplicateAndUpdate()
230 DefBB = DefMI->getParent(); in TailDuplicateAndUpdate()
DLiveIntervalAnalysis.cpp166 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def); in isPartialRedef() local
167 if (DefMI != 0) { in isPartialRedef()
168 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1; in isPartialRedef()
/external/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, in hasRAWHazard() argument
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); in hasRAWHazard()
45 MachineInstr *DefMI = LastMI; in getHazardType() local
55 DefMI = &*I; in getHazardType()
59 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && in getHazardType()
61 hasRAWHazard(DefMI, MI, TRI))) { in getHazardType()
DMLxExpansionPass.cpp92 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI() local
94 if (DefMI->getParent() != MBB) in getAccDefMI()
96 if (DefMI->isCopyLike()) { in getAccDefMI()
97 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
99 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
102 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()
103 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
105 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
111 return DefMI; in getAccDefMI()
160 MachineInstr *DefMI = getAccDefMI(MI); in FindMLxHazard() local
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DARMBaseInstrInfo.cpp1951 MachineInstr *DefMI, unsigned Reg, in FoldImmediate() argument
1954 unsigned DefOpc = DefMI->getOpcode(); in FoldImmediate()
1957 if (!DefMI->getOperand(1).isImm()) in FoldImmediate()
1964 const MCInstrDesc &DefMCID = DefMI->getDesc(); in FoldImmediate()
1967 const MachineOperand &MO = DefMI->getOperand(NumOps-1); in FoldImmediate()
1985 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); in FoldImmediate()
2062 DefMI->eraseFromParent(); in FoldImmediate()
2483 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency() argument
2485 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || in getOperandLatency()
2486 DefMI->isRegSequence() || DefMI->isImplicitDef()) in getOperandLatency()
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DARMBaseInstrInfo.h203 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
211 const MachineInstr *DefMI, unsigned DefIdx,
219 const MachineInstr *DefMI, unsigned DefIdx,
260 const MachineInstr *DefMI, unsigned DefIdx,
263 const MachineInstr *DefMI, unsigned DefIdx) const;
DARMExpandPseudoInsts.cpp55 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
74 MachineInstrBuilder &DefMI) { in TransferImpOps() argument
83 DefMI.addOperand(MO); in TransferImpOps()
/external/llvm/lib/Target/
DTargetInstrInfo.cpp65 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency() argument
70 unsigned DefClass = DefMI->getDesc().getSchedClass(); in getOperandLatency()
85 const MachineInstr *DefMI, in hasLowDefLatency() argument
90 unsigned DefClass = DefMI->getDesc().getSchedClass(); in hasLowDefLatency()
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h637 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, in FoldImmediate() argument
661 const MachineInstr *DefMI, unsigned DefIdx,
672 const MachineInstr *DefMI, unsigned DefIdx, in getOutputLatency() argument
699 const MachineInstr *DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
708 const MachineInstr *DefMI, unsigned DefIdx) const;
/external/llvm/include/llvm/CodeGen/
DLiveRangeEdit.h146 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp457 MachineInstr *DefMI = MRI->getVRegDef(VReg); in EmitSubregNode() local
459 if (DefMI && in EmitSubregNode()
460 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && in EmitSubregNode()
/external/llvm/lib/Target/X86/
DX86InstrInfo.h363 const MachineInstr *DefMI, unsigned DefIdx,
DX86InstrInfo.cpp1318 MachineInstr *DefMI = I.getOperand().getParent(); in regIsPICBase() local
1319 if (DefMI->getOpcode() != X86::MOVPC32r) in regIsPICBase()
1375 MachineInstr *DefMI = I.getOperand().getParent(); in isReallyTriviallyReMaterializable() local
1376 if (DefMI->getOpcode() != X86::MOVPC32r) in isReallyTriviallyReMaterializable()
3799 const MachineInstr *DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
3801 return isHighLatencyDef(DefMI->getOpcode()); in hasHighOperandLatency()