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Searched refs:NewOpc (Results 1 – 15 of 15) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp778 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
779 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) in MergeBaseUpdateLSMultiple()
877 unsigned NewOpc = 0; in MergeBaseUpdateLoadStore() local
895 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub); in MergeBaseUpdateLoadStore()
914 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub); in MergeBaseUpdateLoadStore()
932 BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) in MergeBaseUpdateLoadStore()
941 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
943 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
948 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
955 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
[all …]
DThumb2InstrInfo.cpp439 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in rewriteT2FrameIndex() local
440 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
473 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
483 NewOpc = immediateOffsetOpcode(Opcode); in rewriteT2FrameIndex()
495 NewOpc = negativeOffsetOpcode(Opcode); in rewriteT2FrameIndex()
500 NewOpc = positiveOffsetOpcode(Opcode); in rewriteT2FrameIndex()
521 if (NewOpc != Opcode) in rewriteT2FrameIndex()
522 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
555 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
DARMConstantIslandPass.cpp1723 unsigned NewOpc = 0; in optimizeThumb2Instructions() local
1730 NewOpc = ARM::tLEApcrel; in optimizeThumb2Instructions()
1737 NewOpc = ARM::tLDRpci; in optimizeThumb2Instructions()
1744 if (!NewOpc) in optimizeThumb2Instructions()
1757 U.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Instructions()
1777 unsigned NewOpc = 0; in optimizeThumb2Branches() local
1783 NewOpc = ARM::tB; in optimizeThumb2Branches()
1788 NewOpc = ARM::tBcc; in optimizeThumb2Branches()
1794 if (NewOpc) { in optimizeThumb2Branches()
1799 Br.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Branches()
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DARMISelLowering.cpp2355 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) in LowerINTRINSIC_WO_CHAIN() local
2357 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
4829 unsigned NewOpc = 0; in LowerMUL() local
4834 NewOpc = ARMISD::VMULLs; in LowerMUL()
4839 NewOpc = ARMISD::VMULLu; in LowerMUL()
4844 NewOpc = ARMISD::VMULLs; in LowerMUL()
4847 NewOpc = ARMISD::VMULLu; in LowerMUL()
4851 NewOpc = ARMISD::VMULLu; in LowerMUL()
4856 if (!NewOpc) { in LowerMUL()
4875 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); in LowerMUL()
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DThumb1RegisterInfo.cpp504 unsigned NewOpc = convertToNonSPOpcode(Opcode); in rewriteFrameIndex() local
505 if (NewOpc != Opcode && FrameReg != ARM::SP) in rewriteFrameIndex()
506 MI.setDesc(TII.get(NewOpc)); in rewriteFrameIndex()
DARMExpandPseudoInsts.cpp943 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI() local
945 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMI()
974 unsigned NewOpc = ARM::VSTMDIA; in ExpandMI() local
976 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMI()
1005 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q : in ExpandMI() local
1008 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMI()
DARMISelDAGToDAG.cpp3081 unsigned NewOpc = ARM::LDREXD; in Select() local
3083 NewOpc = ARM::t2LDREXD; in Select()
3097 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(), in Select()
3167 unsigned NewOpc = ARM::STREXD; in Select() local
3169 NewOpc = ARM::t2STREXD; in Select()
3171 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(), in Select()
/external/llvm/lib/Target/CellSPU/
DSPUISelDAGToDAG.cpp609 unsigned NewOpc = 0; in Select() local
623 NewOpc = SPU::AIr32; in Select()
628 NewOpc = SPU::Ar32; in Select()
861 NewOpc = SPU::Ar32; in Select()
867 NewOpc = SPU::AIr32; in Select()
883 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops); in Select()
885 return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops); in Select()
DSPUISelLowering.cpp741 unsigned NewOpc = ISD::ANY_EXTEND; in LowerLOAD() local
744 NewOpc = ISD::FP_EXTEND; in LowerLOAD()
746 result = DAG.getNode(NewOpc, dl, OutVT, result); in LowerLOAD()
/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp219 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) { in LowerSubReg32_Op0() argument
220 OutMI.setOpcode(NewOpc); in LowerSubReg32_Op0()
224 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) { in LowerUnaryToTwoAddr() argument
225 OutMI.setOpcode(NewOpc); in LowerUnaryToTwoAddr()
DX86InstrInfo.cpp2973 unsigned NewOpc = 0; in foldMemoryOperandImpl() local
2977 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; in foldMemoryOperandImpl()
2978 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; in foldMemoryOperandImpl()
2979 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; in foldMemoryOperandImpl()
2980 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; in foldMemoryOperandImpl()
2987 MI->setDesc(get(NewOpc)); in foldMemoryOperandImpl()
3037 unsigned NewOpc = 0; in foldMemoryOperandImpl() local
3040 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; in foldMemoryOperandImpl()
3041 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; in foldMemoryOperandImpl()
3042 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; in foldMemoryOperandImpl()
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/external/llvm/lib/CodeGen/
DMachineLICM.cpp1255 unsigned NewOpc = in ExtractHoistableLoad() local
1260 if (NewOpc == 0) return 0; in ExtractHoistableLoad()
1261 const MCInstrDesc &MID = TII->get(NewOpc); in ExtractHoistableLoad()
DTwoAddressInstructionPass.cpp1288 unsigned NewOpc = in TryInstructionTransform() local
1293 if (NewOpc != 0) { in TryInstructionTransform()
1294 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc); in TryInstructionTransform()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp6674 unsigned NewOpc; in processInstruction() local
6677 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; in processInstruction()
6678 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; in processInstruction()
6679 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; in processInstruction()
6683 TmpInst.setOpcode(NewOpc); in processInstruction()
7135 unsigned NewOpc; in processInstruction() local
7138 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; in processInstruction()
7139 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; in processInstruction()
7140 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; in processInstruction()
7141 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; in processInstruction()
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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp353 unsigned NewOpc = N->getOpcode(); in PromoteIntRes_FP_TO_XINT() local
363 NewOpc = ISD::FP_TO_SINT; in PromoteIntRes_FP_TO_XINT()
365 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); in PromoteIntRes_FP_TO_XINT()