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Searched refs:RegClassInfo (Results 1 – 13 of 13) sorted by relevance

/external/llvm/lib/CodeGen/
DAllocationOrder.cpp27 const RegisterClassInfo &RegClassInfo) in AllocationOrder() argument
28 : Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) { in AllocationOrder()
DAllocationOrder.h40 const RegisterClassInfo &RegClassInfo);
DCriticalAntiDepBreaker.h39 const RegisterClassInfo &RegClassInfo; variable
DRegAllocFast.cpp60 RegisterClassInfo RegClassInfo; member in __anon52dc9a510111::RAFast
516 !RC->contains(Hint) || !RegClassInfo.isAllocatable(Hint))) in allocVirtReg()
532 ArrayRef<unsigned> AO = RegClassInfo.getOrder(RC); in allocVirtReg()
841 if (RegClassInfo.isAllocatable(*I)) in AllocateBasicBlock()
973 if (!RegClassInfo.isAllocatable(Reg)) continue; in AllocateBasicBlock()
1062 if (!RegClassInfo.isAllocatable(Reg)) continue; in AllocateBasicBlock()
1122 RegClassInfo.runOnMachineFunction(Fn); in runOnMachineFunction()
DRegAllocBase.h96 RegisterClassInfo RegClassInfo; variable
DRegisterCoalescer.cpp91 RegisterClassInfo RegClassInfo; member in __anon33c9ccb00111::RegisterCoalescer
1044 unsigned Threshold = RegClassInfo.getNumAllocatableRegs(RC) * 2; in shouldJoinPhys()
1063 unsigned NewRCCount = RegClassInfo.getNumAllocatableRegs(NewRC); in isWinToJoinCrossClass()
1093 unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC); in isWinToJoinCrossClass()
1098 unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC); in isWinToJoinCrossClass()
1394 if (RegClassInfo.isReserved(CP.getDstReg())) { in JoinIntervals()
1814 RegClassInfo.runOnMachineFunction(fn); in runOnMachineFunction()
1847 RegClassInfo.isProperSubClass(MRI->getRegClass(SrcReg))) in runOnMachineFunction()
1850 RegClassInfo.isProperSubClass(MRI->getRegClass(DstReg))) in runOnMachineFunction()
1897 if (RegClassInfo.isProperSubClass(MRI->getRegClass(Reg))) in runOnMachineFunction()
DRegAllocBase.cpp106 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); in init()
209 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
DAggressiveAntiDepBreaker.h122 const RegisterClassInfo &RegClassInfo; variable
DCriticalAntiDepBreaker.cpp35 RegClassInfo(RCI), in CriticalAntiDepBreaker()
404 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
553 if (!RegClassInfo.isAllocatable(AntiDepReg)) in BreakAntiDependencies()
DPostRASchedulerList.cpp83 RegisterClassInfo RegClassInfo; member in __anon8f8ffdce0111::PostRAScheduler
257 RegClassInfo.runOnMachineFunction(Fn); in runOnMachineFunction()
286 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode, in runOnMachineFunction()
DAggressiveAntiDepBreaker.cpp124 RegClassInfo(RCI), in AggressiveAntiDepBreaker()
623 ArrayRef<unsigned> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
642 if (!RegClassInfo.isAllocatable(NewSuperReg)) continue; in FindSuitableFreeRegisters()
826 if (!RegClassInfo.isAllocatable(AntiDepReg)) { in BreakAntiDependencies()
DRegAllocBasic.cpp247 RegClassInfo.getOrder(MRI->getRegClass(VirtReg.reg)); in selectOrSplit()
DRegAllocGreedy.cpp646 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg)) in tryEvict()
966 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in splitAroundRegion()
1233 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in tryBlockSplit()
1608 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo); in selectOrSplit()