| /external/llvm/lib/Target/Sparc/ |
| D | DelaySlotFiller.cpp | 223 if (MO.isUse()) { in delayHasHazard()
245 assert(Reg.isUse() && "JMPL first operand is not a use."); in insertCallUses()
252 assert(RegOrImm.isUse() && "JMPLrr second operand is not a use."); in insertCallUses()
273 if (MO.isUse()) in insertDefsUses()
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| /external/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 215 if (MO.isUse() && MOReg != SavedReg) in Sink3AddrInstruction()
371 if (MO.isUse() && DI->second < LastUse) in NoUseAfterLastDef()
397 if (MO.isUse() && DI->second > LastUseDist) { in FindLastUseInMBB()
475 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
829 if (MO.isUse() && MO.isKill()) in isSafeToDelete()
1021 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in RescheduleMIBelowKill()
1091 if (MO.isUse()) { in RescheduleKillAboveMI()
1129 if (MO.isUse()) { in RescheduleKillAboveMI()
1174 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in RescheduleKillAboveMI()
1339 if (MO.isUse()) { in TryInstructionTransform()
[all …]
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| D | MachineInstr.cpp | 950 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
991 if (!MO.isReg() || !MO.isUse()) in findRegisterUseOperandIdx()
1023 if (MO.isUse()) in readsWritesVirtualRegister()
1109 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse()) in isRegTiedToUseOperand()
1126 if (MO.isReg() && MO.isUse() && in isRegTiedToUseOperand()
1143 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0) in isRegTiedToDefOperand()
1177 if (!MO.isReg() || !MO.isUse()) in isRegTiedToDefOperand()
1192 if (MO.isReg() && MO.isUse()) in clearKillInfo()
1302 if (MO.isUse()) in isSafeToReMat()
1411 if (!MO.isReg() || MO.isUse()) in allDefsAreDead()
[all …]
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| D | Spiller.cpp | 113 hasUse |= mi->getOperand(i).isUse(); in trivialSpillEverywhere()
127 if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) { in trivialSpillEverywhere()
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| D | ExpandPostRAPseudos.cpp | 90 if (!MO.isReg() || !MO.isImplicit() || MO.isUse()) in TransferImplicitDefs()
100 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
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| D | RegAllocFast.cpp | 224 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { in addKillFlag()
596 if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse()) in defineVirtReg()
628 if (MO.isUse()) in reloadVirtReg()
724 if (MO.isUse()) { in handleThroughOperands()
806 if (!MO.isReg() || !MO.isUse()) in addRetOperands()
962 if (MO.isUse()) { in AllocateBasicBlock()
974 if (MO.isUse()) { in AllocateBasicBlock()
1010 if (MO.isUse()) { in AllocateBasicBlock()
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| D | TargetInstrInfoImpl.cpp | 367 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!"); in foldMemoryOperand()
439 if (MO.isUse()) { in isReallyTriviallyReMaterializableGeneric()
460 if (MO.isUse()) in isReallyTriviallyReMaterializableGeneric()
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| D | MachineCSE.cpp | 123 if (!MO.isReg() || !MO.isUse()) in INITIALIZE_PASS_DEPENDENCY()
179 if (MO.isUse()) in isPhysDefTriviallyDead()
344 if (MO.isReg() && MO.isUse() && in isProfitableToCSE()
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| D | CriticalAntiDepBreaker.cpp | 236 if (MO.isUse() && Special) { in PrescanInstruction()
307 if (!MO.isUse()) continue; in ScanInstruction()
606 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { in BreakAntiDependencies()
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| D | RegisterScavenging.cpp | 161 if (MO.isUse()) { in forward()
185 if (MO.isUse()) { in forward()
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| D | DeadMachineInstructionElim.cpp | 187 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
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| D | MachineSink.cpp | 483 if (MO.isUse()) { in FindSuccToSinkTo()
495 if (MO.isUse()) continue; in FindSuccToSinkTo()
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| D | BranchFolding.cpp | 155 if (!MO.isReg() || !MO.isUse()) in OptimizeImpDefsBlock()
1485 if (MO.isUse()) { in findHoistingInsertPosAndDeps()
1513 if (!MO.isReg() || MO.isUse()) in findHoistingInsertPosAndDeps()
1547 if (MO.isUse()) { in findHoistingInsertPosAndDeps()
1681 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) in HoistCommonCodeInSuccs()
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| D | PostRASchedulerList.cpp | 531 if (!MO.isReg() || !MO.isUse()) continue; in FixupKills()
567 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue; in FixupKills()
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| D | LiveInterval.cpp | 715 if (MO.isUse() && MO.isUndef()) in Distribute()
719 Idx = Idx.getRegSlot(MO.isUse()); in Distribute()
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| D | MachineLICM.cpp | 934 if (MO.isUse()) { in IsLoopInvariantInst()
952 if (!MO.isUse()) in IsLoopInvariantInst()
1023 if (!MO.isReg() || !MO.isUse()) in HasHighOperandLatency()
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| D | ScheduleDAGInstrs.cpp | 287 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; in addPhysRegDeps()
786 if (!MO.isReg() || !MO.isUse()) in computeOperandLatency()
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| D | InlineSpiller.cpp | 844 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) in reMaterializeFor()
898 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) { in reMaterializeFor()
1195 if (MO.isUse()) { in spillAroundUses()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsDelaySlotFiller.cpp | 206 if (MO.isUse()) { in delayHasHazard()
237 else if (MO.isUse()) in insertDefsUses()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 455 if ((!ReturnUses && op->isUse()) || in defusechain_iterator()
487 while (Op && ((!ReturnUses && Op->isUse()) ||
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| D | MachineOperand.h | 247 bool isUse() const { in isUse() function
301 return !isUndef() && !isInternalRead() && (isUse() || getSubReg()); in readsReg()
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| D | ScheduleDAGInstrs.h | 81 if (!MO.isReg() || !MO.isUse()) in VisitRegion()
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| D | LiveIntervalAnalysis.h | 102 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2ITBlockPass.cpp | 70 if (MO.isUse()) in TrackDefUses()
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| D | Thumb2SizeReduction.cpp | 230 if (!MO.isReg() || MO.isUndef() || MO.isUse()) in canAddPseudoFlagDep()
813 if (!MO.isReg() || MO.isUndef() || MO.isUse()) in UpdateCPSRDef()
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