| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 196 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32 , Custom); in NVPTXTargetLowering()
197 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32 , Custom); in NVPTXTargetLowering()
198 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i16 , Custom); in NVPTXTargetLowering()
199 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i8 , Custom); in NVPTXTargetLowering()
200 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64 , Custom); in NVPTXTargetLowering()
201 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64 , Custom); in NVPTXTargetLowering()
202 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i32 , Custom); in NVPTXTargetLowering()
203 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f32 , Custom); in NVPTXTargetLowering()
204 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i16 , Custom); in NVPTXTargetLowering()
205 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i8 , Custom); in NVPTXTargetLowering()
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| /external/llvm/test/CodeGen/X86/ |
| D | widen_shuffle-1.ll | 53 ; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS
62 ; PR11389: another CONCAT_VECTORS case
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 368 case ISD::CONCAT_VECTORS: in ScalarizeVectorOperand()
482 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; in SplitVectorResult()
676 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size()); in SplitVecRes_CONCAT_VECTORS()
679 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size()); in SplitVecRes_CONCAT_VECTORS()
1028 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; in SplitVectorOperand()
1081 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
1237 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes); in SplitVecOp_VSETCC()
1256 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in SplitVecOp_FP_ROUND()
1287 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break; in WidenVectorResult()
1502 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl, in WidenVecRes_Binary()
[all …]
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| D | SelectionDAGDumper.cpp | 193 case ISD::CONCAT_VECTORS: return "concat_vectors"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 90 case ISD::CONCAT_VECTORS: in PromoteIntegerResult()
602 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); in PromoteIntRes_TRUNCATE()
764 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; in PromoteIntegerOperand()
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| D | SelectionDAGBuilder.cpp | 261 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, in getCopyFromPartsVector()
2880 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), in visitShuffleVector()
2888 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), in visitShuffleVector()
2905 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, in visitShuffleVector()
2908 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, in visitShuffleVector()
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| D | SelectionDAG.cpp | 2539 case ISD::CONCAT_VECTORS: in getNode()
2749 case ISD::CONCAT_VECTORS: in getNode()
2941 N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
3203 case ISD::CONCAT_VECTORS: in getNode()
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| D | TargetLowering.cpp | 537 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); in TargetLowering()
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| D | LegalizeDAG.cpp | 2830 case ISD::CONCAT_VECTORS: { in ExpandNode()
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| D | DAGCombiner.cpp | 1156 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); in visit()
8105 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, in visitBUILD_VECTOR()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 269 CONCAT_VECTORS, enumerator
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 1152 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in X86TargetLowering()
4465 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1); in PromoteSplat()
6261 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]); in LowerVECTOR_SHUFFLE_256()
8749 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, in Lower256IntVSETCC()
10618 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, in Lower256IntArith()
10906 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); in LowerShift()
11027 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2); in LowerSIGN_EXTEND_INREG()
11274 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
13397 if (V1.getOpcode() == ISD::CONCAT_VECTORS && in PerformShuffleCombine256()
13398 V2.getOpcode() == ISD::CONCAT_VECTORS) { in PerformShuffleCombine256()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 121 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
5062 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
5097 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
5253 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
8133 if (Op0.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
8134 Op1.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
8151 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, in PerformVECTOR_SHUFFLECombine()
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| D | ARMISelDAGToDAG.cpp | 3305 case ISD::CONCAT_VECTORS: in Select()
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