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Searched refs:DestReg (Results 1 – 25 of 51) sorted by relevance

123

/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp38 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
40 if (NVPTX::Int32RegsRegClass.contains(DestReg) && in copyPhysReg()
42 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg) in copyPhysReg()
44 else if (NVPTX::Int8RegsRegClass.contains(DestReg) && in copyPhysReg()
46 BuildMI(MBB, I, DL, get(NVPTX::IMOV8rr), DestReg) in copyPhysReg()
48 else if (NVPTX::Int1RegsRegClass.contains(DestReg) && in copyPhysReg()
50 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg) in copyPhysReg()
52 else if (NVPTX::Float32RegsRegClass.contains(DestReg) && in copyPhysReg()
54 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg) in copyPhysReg()
56 else if (NVPTX::Int16RegsRegClass.contains(DestReg) && in copyPhysReg()
[all …]
DNVPTXInstrInfo.h55 unsigned DestReg, unsigned SrcReg,
59 unsigned &DestReg) const;
/external/llvm/lib/Target/Hexagon/
DHexagonSplitTFRCondSets.cpp89 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
105 if (DestReg != SrcReg1) { in runOnMachineFunction()
107 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); in runOnMachineFunction()
109 if (DestReg != SrcReg2) { in runOnMachineFunction()
111 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); in runOnMachineFunction()
119 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
124 if (DestReg != SrcReg1) { in runOnMachineFunction()
126 TII->get(Hexagon::TFR_cPt), DestReg). in runOnMachineFunction()
131 TII->get(Hexagon::TFRI_cNotPt), DestReg). in runOnMachineFunction()
136 TII->get(Hexagon::TFRI_cNotPt_f), DestReg). in runOnMachineFunction()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp415 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
418 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
420 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
422 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
424 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
426 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
428 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
435 BuildMI(MBB, I, DL, MCID, DestReg) in copyPhysReg()
438 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
614 unsigned DestReg, int FrameIdx, in LoadRegFromStackSlot() argument
[all …]
DPPCInstrInfo.h76 unsigned DestReg, int FrameIdx,
123 unsigned DestReg, unsigned SrcReg,
134 unsigned DestReg, int FrameIndex,
/external/llvm/lib/Target/ARM/
DThumb1RegisterInfo.cpp68 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool() argument
79 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
93 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmInReg() argument
99 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
110 unsigned LdReg = DestReg; in emitThumbRegPlusImmInReg()
111 if (DestReg == ARM::SP) { in emitThumbRegPlusImmInReg()
131 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmInReg()
134 if (DestReg == ARM::SP || isSub) in emitThumbRegPlusImmInReg()
170 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmediate() argument
186 if (DestReg == BaseReg && BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
[all …]
DThumb1InstrInfo.cpp43 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
45 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
81 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
85 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
86 isARMLowRegister(DestReg))) && "Unknown regclass!"); in loadRegFromStackSlot()
89 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
90 isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) in loadRegFromStackSlot()
DThumb2InstrInfo.cpp114 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
118 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
153 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
169 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
174 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI); in loadRegFromStackSlot()
179 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
187 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
193 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg) in emitT2RegPlusImmediate()
[all …]
DARMBaseInstrInfo.cpp648 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
650 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
654 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
659 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
669 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
671 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
675 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg()
689 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
691 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
694 else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
[all …]
DARMBaseInstrInfo.h111 unsigned DestReg, unsigned SrcReg,
122 unsigned DestReg, int FrameIndex,
136 unsigned DestReg, unsigned SubIdx,
378 unsigned DestReg, unsigned BaseReg, int NumBytes,
384 unsigned DestReg, unsigned BaseReg, int NumBytes,
389 unsigned DestReg, unsigned BaseReg,
DThumb1InstrInfo.h44 unsigned DestReg, unsigned SrcReg,
54 unsigned DestReg, int FrameIndex,
DThumb2RegisterInfo.cpp38 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool() argument
49 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
DThumb2InstrInfo.h45 unsigned DestReg, unsigned SrcReg,
56 unsigned DestReg, int FrameIndex,
/external/llvm/lib/CodeGen/
DStrongPHIElimination.cpp243 unsigned DestReg = BBI->getOperand(0).getReg(); in runOnMachineFunction() local
244 addReg(DestReg); in runOnMachineFunction()
251 unionRegs(DestReg, SrcReg); in runOnMachineFunction()
287 unsigned DestReg = BBI->getOperand(0).getReg(); in runOnMachineFunction() local
288 addReg(DestReg); in runOnMachineFunction()
293 unionRegs(DestReg, SrcReg); in runOnMachineFunction()
317 unsigned DestReg = PHI->getOperand(0).getReg(); in runOnMachineFunction() local
318 if (!InsertedDestCopies.count(DestReg)) in runOnMachineFunction()
319 MergeLIsAndRename(DestReg, NewReg); in runOnMachineFunction()
340 unsigned DestReg = I->first; in runOnMachineFunction() local
[all …]
DPHIElimination.cpp209 unsigned DestReg = MPhi->getOperand(0).getReg(); in LowerAtomicPHINode() local
226 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg); in LowerAtomicPHINode()
238 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); in LowerAtomicPHINode()
242 TII->get(TargetOpcode::COPY), DestReg) in LowerAtomicPHINode()
281 LV->addVirtualRegisterDead(DestReg, PHICopy); in LowerAtomicPHINode()
282 LV->removeVirtualRegisterDead(DestReg, MPhi); in LowerAtomicPHINode()
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp87 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
91 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
104 if (Mips::CCRRegClass.contains(DestReg)) in copyPhysReg()
106 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()
108 else if (DestReg == Mips::HI) in copyPhysReg()
109 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
110 else if (DestReg == Mips::LO) in copyPhysReg()
111 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
113 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
115 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
[all …]
DMips16InstrInfo.cpp59 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
63 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
72 if (DestReg) in copyPhysReg()
73 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
92 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
DMips16InstrInfo.h48 unsigned DestReg, unsigned SrcReg,
59 unsigned DestReg, int FrameIndex,
DMipsSEInstrInfo.h49 unsigned DestReg, unsigned SrcReg,
60 unsigned DestReg, int FrameIndex,
/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h207 unsigned DestReg) { in BuildMI() argument
209 .addReg(DestReg, RegState::Define); in BuildMI()
220 unsigned DestReg) { in BuildMI() argument
223 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define); in BuildMI()
230 unsigned DestReg) { in BuildMI() argument
233 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define); in BuildMI()
240 unsigned DestReg) { in BuildMI() argument
243 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
247 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
302 unsigned DestReg) { in BuildMI() argument
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp282 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
284 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
285 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
287 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
288 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
290 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
291 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg) in copyPhysReg()
321 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
328 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
330 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp64 unsigned DestReg, int FrameIdx, in loadRegFromStackSlot() argument
80 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
90 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
93 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
95 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
100 BuildMI(MBB, I, DL, get(Opc), DestReg) in copyPhysReg()
DMSP430InstrInfo.h56 unsigned DestReg, unsigned SrcReg,
67 unsigned DestReg, int FrameIdx,
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp336 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
338 bool GRDest = XCore::GRRegsRegClass.contains(DestReg); in copyPhysReg()
342 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) in copyPhysReg()
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); in copyPhysReg()
353 if (DestReg == XCore::SP && GRSrc) { in copyPhysReg()
378 unsigned DestReg, int FrameIndex, in loadRegFromStackSlot() argument
384 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) in loadRegFromStackSlot()
/external/llvm/lib/Target/CellSPU/
DSPUInstrInfo.h49 unsigned DestReg, unsigned SrcReg,
62 unsigned DestReg, int FrameIndex,

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