Searched refs:FMA (Results 1 – 23 of 23) sorted by relevance
1 … < %s -mtriple=i386-apple-darwin10 -mattr=+fma,-fma4 | FileCheck %s --check-prefix=CHECK-FMA-INST2 … < %s -mtriple=i386-apple-darwin10 -mattr=-fma,-fma4 | FileCheck %s --check-prefix=CHECK-FMA-CALL3 … < %s -mtriple=x86_64-apple-darwin10 -mattr=+fma,-fma4 | FileCheck %s --check-prefix=CHECK-FMA-INST4 …< %s -mtriple=x86_64-apple-darwin10 -mattr=-fma,-fma4 | FileCheck %s --check-prefix=CHECK-FMA-CALL5 ; RUN: llc < %s -march=x86 -mcpu=bdver2 -mattr=-fma4 | FileCheck %s --check-prefix=CHECK-FMA-INST6 ; RUN: llc < %s -march=x86 -mcpu=bdver2 -mattr=-fma,-fma4 | FileCheck %s --check-prefix=CHECK-FMA-C…9 ; CHECK-FMA-INST: vfmadd213ss10 ; CHECK-FMA-CALL: fmaf19 ; CHECK-FMA-INST: vfmadd213sd20 ; CHECK-FMA-CALL: fma
1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA3 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA8 ; FMA: fma.rn.f3218 ; FMA: fma.rn.f64
234 FADD, FSUB, FMUL, FMA, FDIV, FREM, enumerator
1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//10 // This file describes FMA (Fused Multiply-Add) instructions.
664 setOperationAction(ISD::FMA, MVT::f64, Expand); in X86TargetLowering()665 setOperationAction(ISD::FMA, MVT::f32, Expand); in X86TargetLowering()697 setOperationAction(ISD::FMA, MVT::f80, Expand); in X86TargetLowering()738 setOperationAction(ISD::FMA, (MVT::SimpleValueType)VT, Expand); in X86TargetLowering()1074 setOperationAction(ISD::FMA, MVT::v8f32, Custom); in X86TargetLowering()1075 setOperationAction(ISD::FMA, MVT::v4f64, Custom); in X86TargetLowering()1076 setOperationAction(ISD::FMA, MVT::v4f32, Custom); in X86TargetLowering()1077 setOperationAction(ISD::FMA, MVT::v2f64, Custom); in X86TargetLowering()1078 setOperationAction(ISD::FMA, MVT::f32, Custom); in X86TargetLowering()1079 setOperationAction(ISD::FMA, MVT::f64, Custom); in X86TargetLowering()[all …]
1668 // FMA - Fused Multiply-Add support (requires FMA)
28 …me:PM_FPU_FLOP_GRP2 : (Group 2 pm_compat_utilization2) FPU executed 1FLOP, FMA, FSQRT or FDIV inst…
180 case ISD::FMA: return "fma"; in getOperationName()
224 case ISD::FMA: in LegalizeOp()
78 case ISD::FMA: R = SoftenFloatRes_FMA(N); break; in SoftenFloatResult()861 case ISD::FMA: ExpandFloatRes_FMA(N, Lo, Hi); break; in ExpandFloatResult()
1133 case ISD::FMA: return visitFMA(N); in visit()5819 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { in visitFADD()5823 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, in visitFADD()5830 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, in visitFADD()5897 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { in visitFSUB()5901 return DAG.getNode(ISD::FMA, dl, VT, in visitFSUB()5909 return DAG.getNode(ISD::FMA, dl, VT, in visitFSUB()5921 return DAG.getNode(ISD::FMA, dl, VT, in visitFSUB()6010 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2); in visitFMA()6026 return DAG.getNode(ISD::FMA, dl, VT, in visitFMA()
118 case ISD::FMA: in ScalarizeVectorResult()554 case ISD::FMA: in SplitVectorResult()1369 case ISD::FMA: in WidenVectorResult()
4977 setValue(&I, DAG.getNode(ISD::FMA, dl, in visitIntrinsicCall()4986 TLI.isOperationLegal(ISD::FMA, VT) && in visitIntrinsicCall()4988 setValue(&I, DAG.getNode(ISD::FMA, dl, in visitIntrinsicCall()
3046 case ISD::FMA: in ExpandNode()
763 setOperationAction(ISD::FMA , MVT::f64, Expand); in SparcTargetLowering()767 setOperationAction(ISD::FMA , MVT::f32, Expand); in SparcTargetLowering()
73 setOperationAction(ISD::FMA, MVT::f32, Expand); in MBlazeTargetLowering()
222 setOperationAction(ISD::FMA, MVT::f64, Expand); in SPUTargetLowering()223 setOperationAction(ISD::FMA, MVT::f32, Expand); in SPUTargetLowering()
746 …0 name:PM_FPU0_FLOP_GRP121 : (Group 121 pm_fpu0_misc) FPU0 executed 1FLOP, FMA, FSQRT or FDIV inst…770 …0 name:PM_FPU1_FLOP_GRP125 : (Group 125 pm_fpu1_misc) FPU1 executed 1FLOP, FMA, FSQRT or FDIV inst…791 …1000 name:PM_FPU_FLOP_GRP128 : (Group 128 pm_fpu_flop) FPU executed 1FLOP, FMA, FSQRT or FDIV inst…
238 setOperationAction(ISD::FMA, MVT::f32, Expand); in MipsTargetLowering()239 setOperationAction(ISD::FMA, MVT::f64, Expand); in MipsTargetLowering()
371 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>;
137 setOperationAction(ISD::FMA , MVT::f64, Legal); in PPCTargetLowering()142 setOperationAction(ISD::FMA , MVT::f32, Legal); in PPCTargetLowering()383 setOperationAction(ISD::FMA, MVT::v4f32, Legal); in PPCTargetLowering()
958 If a target supports floating point multiply-and-add (FMA) operations, one of2408 * Arithmetic instruction selection (including combo FMA)
775 setOperationAction(ISD::FMA, MVT::f64, Expand); in ARMTargetLowering()776 setOperationAction(ISD::FMA, MVT::f32, Expand); in ARMTargetLowering()