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Searched refs:MVT (Results 1 – 25 of 113) sorted by relevance

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/external/llvm/lib/VMCore/
DValueTypes.cpp107 case MVT::i1: return "i1"; in getEVTString()
108 case MVT::i8: return "i8"; in getEVTString()
109 case MVT::i16: return "i16"; in getEVTString()
110 case MVT::i32: return "i32"; in getEVTString()
111 case MVT::i64: return "i64"; in getEVTString()
112 case MVT::i128: return "i128"; in getEVTString()
113 case MVT::f16: return "f16"; in getEVTString()
114 case MVT::f32: return "f32"; in getEVTString()
115 case MVT::f64: return "f64"; in getEVTString()
116 case MVT::f80: return "f80"; in getEVTString()
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/external/llvm/include/llvm/CodeGen/
DValueTypes.h33 class MVT {
146 MVT() : SimpleTy((SimpleValueType)(INVALID_SIMPLE_VALUE_TYPE)) {} in MVT() function
147 MVT(SimpleValueType SVT) : SimpleTy(SVT) { } in MVT() function
149 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
150 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
151 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
152 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
153 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
154 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
158 return ((SimpleTy >= MVT::FIRST_FP_VALUETYPE && in isFloatingPoint()
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DFastISel.h163 virtual unsigned FastEmit_(MVT VT,
164 MVT RetVT,
171 virtual unsigned FastEmit_r(MVT VT,
172 MVT RetVT,
180 virtual unsigned FastEmit_rr(MVT VT,
181 MVT RetVT,
190 virtual unsigned FastEmit_ri(MVT VT,
191 MVT RetVT,
200 virtual unsigned FastEmit_rf(MVT VT,
201 MVT RetVT,
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DCallingConvLower.h61 MVT ValVT;
64 MVT LocVT;
67 static CCValAssign getReg(unsigned ValNo, MVT ValVT, in getReg()
68 unsigned RegNo, MVT LocVT, in getReg()
81 static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, in getCustomReg()
82 unsigned RegNo, MVT LocVT, in getCustomReg()
90 static CCValAssign getMem(unsigned ValNo, MVT ValVT, in getMem()
91 unsigned Offset, MVT LocVT, in getMem()
104 static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, in getCustomMem()
105 unsigned Offset, MVT LocVT, in getCustomMem()
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/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp173 MVT SimpleVT = LoadedVT.getSimpleVT(); in SelectLoad()
191 MVT ScalarVT = SimpleVT.getScalarType(); in SelectLoad()
207 MVT::SimpleValueType TargetVT = LD->getValueType(0).getSimpleVT().SimpleTy; in SelectLoad()
211 case MVT::i8: Opcode = NVPTX::LD_i8_avar; break; in SelectLoad()
212 case MVT::i16: Opcode = NVPTX::LD_i16_avar; break; in SelectLoad()
213 case MVT::i32: Opcode = NVPTX::LD_i32_avar; break; in SelectLoad()
214 case MVT::i64: Opcode = NVPTX::LD_i64_avar; break; in SelectLoad()
215 case MVT::f32: Opcode = NVPTX::LD_f32_avar; break; in SelectLoad()
216 case MVT::f64: Opcode = NVPTX::LD_f64_avar; break; in SelectLoad()
217 case MVT::v2i8: Opcode = NVPTX::LD_v2i8_avar; break; in SelectLoad()
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DNVPTXISelLowering.cpp82 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass); in NVPTXTargetLowering()
83 addRegisterClass(MVT::i8, &NVPTX::Int8RegsRegClass); in NVPTXTargetLowering()
84 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass); in NVPTXTargetLowering()
85 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
86 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass); in NVPTXTargetLowering()
87 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass); in NVPTXTargetLowering()
88 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass); in NVPTXTargetLowering()
91 addRegisterClass(MVT::v2f32, &NVPTX::V2F32RegsRegClass); in NVPTXTargetLowering()
92 addRegisterClass(MVT::v4f32, &NVPTX::V4F32RegsRegClass); in NVPTXTargetLowering()
93 addRegisterClass(MVT::v2i32, &NVPTX::V2I32RegsRegClass); in NVPTXTargetLowering()
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/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp52 CC_Hexagon(unsigned ValNo, MVT ValVT,
53 MVT LocVT, CCValAssign::LocInfo LocInfo,
57 CC_Hexagon32(unsigned ValNo, MVT ValVT,
58 MVT LocVT, CCValAssign::LocInfo LocInfo,
62 CC_Hexagon64(unsigned ValNo, MVT ValVT,
63 MVT LocVT, CCValAssign::LocInfo LocInfo,
67 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
68 MVT LocVT, CCValAssign::LocInfo LocInfo,
72 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
73 MVT LocVT, CCValAssign::LocInfo LocInfo,
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DHexagonISelDAGToDAG.cpp278 if (MemType == MVT::i64 && isShiftedInt<11,3>(Offset)) { in OffsetFitsS11()
281 if (MemType == MVT::i32 && isShiftedInt<11,2>(Offset)) { in OffsetFitsS11()
284 if (MemType == MVT::i16 && isShiftedInt<11,1>(Offset)) { in OffsetFitsS11()
287 if (MemType == MVT::i8 && isInt<11>(Offset)) { in OffsetFitsS11()
310 MVT PointerTy = TLI.getPointerTy(); in SelectBaseOffsetLoad()
319 if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed; in SelectBaseOffsetLoad()
320 else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed; in SelectBaseOffsetLoad()
321 else if (LoadedVT == MVT::i16) Opcode = Hexagon::LDrih_indexed; in SelectBaseOffsetLoad()
322 else if (LoadedVT == MVT::i8) Opcode = Hexagon::LDrib_indexed; in SelectBaseOffsetLoad()
329 MVT::Other, in SelectBaseOffsetLoad()
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/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp41 if (VT==MVT::i1) retval=3; in prefslotOffset()
42 if (VT==MVT::i8) retval=3; in prefslotOffset()
43 if (VT==MVT::i16) retval=2; in prefslotOffset()
105 addRegisterClass(MVT::i8, &SPU::R8CRegClass); in SPUTargetLowering()
106 addRegisterClass(MVT::i16, &SPU::R16CRegClass); in SPUTargetLowering()
107 addRegisterClass(MVT::i32, &SPU::R32CRegClass); in SPUTargetLowering()
108 addRegisterClass(MVT::i64, &SPU::R64CRegClass); in SPUTargetLowering()
109 addRegisterClass(MVT::f32, &SPU::R32FPRegClass); in SPUTargetLowering()
110 addRegisterClass(MVT::f64, &SPU::R64FPRegClass); in SPUTargetLowering()
111 addRegisterClass(MVT::i128, &SPU::GPRCRegClass); in SPUTargetLowering()
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DSPUISelDAGToDAG.cpp82 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) { in isIntS16Immediate()
84 } else if (vt == MVT::i32) { in isIntS16Immediate()
98 if (vt == MVT::f32) { in isFPS16Immediate()
115 ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32)); in getCarryGenerateShufMask()
116 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32)); in getCarryGenerateShufMask()
117 ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32)); in getCarryGenerateShufMask()
118 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32)); in getCarryGenerateShufMask()
120 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in getCarryGenerateShufMask()
130 ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32)); in getBorrowGenerateShufMask()
131 ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32)); in getBorrowGenerateShufMask()
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/external/llvm/utils/TableGen/
DCodeGenTarget.cpp37 MVT::SimpleValueType llvm::getValueType(Record *Rec) { in getValueType()
38 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); in getValueType()
41 std::string llvm::getName(MVT::SimpleValueType T) { in getName()
43 case MVT::Other: return "UNKNOWN"; in getName()
44 case MVT::iPTR: return "TLI.getPointerTy()"; in getName()
45 case MVT::iPTRAny: return "TLI.getPointerTy()"; in getName()
50 std::string llvm::getEnumName(MVT::SimpleValueType T) { in getEnumName()
52 case MVT::Other: return "MVT::Other"; in getEnumName()
53 case MVT::i1: return "MVT::i1"; in getEnumName()
54 case MVT::i8: return "MVT::i8"; in getEnumName()
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/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp36 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_SRet()
37 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_SRet()
49 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_f64()
50 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_f64()
135 SDValue RetAddrOffsetNode = DAG.getConstant(RetAddrOffset, MVT::i32); in LowerReturn()
138 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, in LowerReturn()
140 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, in LowerReturn()
174 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); in LowerFormalArguments()
175 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, in LowerFormalArguments()
184 assert(VA.getLocVT() == MVT::f64); in LowerFormalArguments()
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/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp63 return CurDAG->getTargetConstant(Imm, MVT::i32); in getI32Imm()
69 return CurDAG->getTargetConstant(Imm, MVT::i64); in getI64Imm()
257 if (PPCLowering.getPointerTy() == MVT::i32) { in getGlobalBaseReg()
280 if (N->getValueType(0) == MVT::i32) in isIntS16Immediate()
294 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { in isInt32Immediate()
304 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { in isInt64Immediate()
352 if (N->getValueType(0) != MVT::i32) in isRotateAndMask()
454 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); in SelectBitfieldInsert()
467 if (LHS.getValueType() == MVT::i32) { in SelectCC()
473 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, in SelectCC()
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DPPCISelLowering.cpp39 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
43 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
44 MVT &LocVT,
48 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
49 MVT &LocVT,
83 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
84 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
85 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
88 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in PPCTargetLowering()
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); in PPCTargetLowering()
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/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp69 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); in XCoreTargetLowering()
86 setOperationAction(ISD::BR_CC, MVT::Other, Expand); in XCoreTargetLowering()
87 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in XCoreTargetLowering()
88 setOperationAction(ISD::ADDC, MVT::i32, Expand); in XCoreTargetLowering()
89 setOperationAction(ISD::ADDE, MVT::i32, Expand); in XCoreTargetLowering()
90 setOperationAction(ISD::SUBC, MVT::i32, Expand); in XCoreTargetLowering()
91 setOperationAction(ISD::SUBE, MVT::i32, Expand); in XCoreTargetLowering()
94 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in XCoreTargetLowering()
97 setOperationAction(ISD::ADD, MVT::i64, Custom); in XCoreTargetLowering()
98 setOperationAction(ISD::SUB, MVT::i64, Custom); in XCoreTargetLowering()
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DXCoreISelDAGToDAG.cpp55 return CurDAG->getTargetConstant(Imm, MVT::i32); in getI32Imm()
95 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); in SelectADDRspii()
96 Offset = CurDAG->getTargetConstant(0, MVT::i32); in SelectADDRspii()
105 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); in SelectADDRspii()
106 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); in SelectADDRspii()
117 Offset = CurDAG->getTargetConstant(0, MVT::i32); in SelectADDRdpii()
127 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); in SelectADDRdpii()
138 Offset = CurDAG->getTargetConstant(0, MVT::i32); in SelectADDRcpii()
148 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); in SelectADDRcpii()
166 MVT::i32, MskSize); in Select()
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/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp109 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass); in MipsTargetLowering()
112 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass); in MipsTargetLowering()
115 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); in MipsTargetLowering()
116 addRegisterClass(MVT::i32, &Mips::CPURARegRegClass); in MipsTargetLowering()
120 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); in MipsTargetLowering()
125 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); in MipsTargetLowering()
127 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); in MipsTargetLowering()
132 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); in MipsTargetLowering()
133 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in MipsTargetLowering()
134 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in MipsTargetLowering()
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/external/llvm/lib/Target/MBlaze/
DMBlazeISelLowering.cpp38 static bool CC_MBlaze_AssignReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
65 addRegisterClass(MVT::i32, &MBlaze::GPRRegClass); in MBlazeTargetLowering()
67 addRegisterClass(MVT::f32, &MBlaze::GPRRegClass); in MBlazeTargetLowering()
68 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in MBlazeTargetLowering()
72 setOperationAction(ISD::FREM, MVT::f32, Expand); in MBlazeTargetLowering()
73 setOperationAction(ISD::FMA, MVT::f32, Expand); in MBlazeTargetLowering()
74 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Expand); in MBlazeTargetLowering()
75 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Expand); in MBlazeTargetLowering()
76 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in MBlazeTargetLowering()
77 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); in MBlazeTargetLowering()
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/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp167 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; in X86TargetLowering()
224 addRegisterClass(MVT::i8, &X86::GR8RegClass); in X86TargetLowering()
225 addRegisterClass(MVT::i16, &X86::GR16RegClass); in X86TargetLowering()
226 addRegisterClass(MVT::i32, &X86::GR32RegClass); in X86TargetLowering()
228 addRegisterClass(MVT::i64, &X86::GR64RegClass); in X86TargetLowering()
230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in X86TargetLowering()
233 setTruncStoreAction(MVT::i64, MVT::i32, Expand); in X86TargetLowering()
234 setTruncStoreAction(MVT::i64, MVT::i16, Expand); in X86TargetLowering()
235 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); in X86TargetLowering()
236 setTruncStoreAction(MVT::i32, MVT::i16, Expand); in X86TargetLowering()
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/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp67 addRegisterClass(MVT::i8, &MSP430::GR8RegClass); in MSP430TargetLowering()
68 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); in MSP430TargetLowering()
83 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
84 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); in MSP430TargetLowering()
90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); in MSP430TargetLowering()
93 setTruncStoreAction(MVT::i16, MVT::i8, Expand); in MSP430TargetLowering()
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/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp79 DecodePSHUFMask(MVT::v4i32, MI->getOperand(MI->getNumOperands()-1).getImm(), in EmitAnyX86InstComments()
87 DecodePSHUFMask(MVT::v8i32, MI->getOperand(MI->getNumOperands()-1).getImm(), in EmitAnyX86InstComments()
99 DecodePSHUFHWMask(MVT::v8i16, in EmitAnyX86InstComments()
108 DecodePSHUFHWMask(MVT::v16i16, in EmitAnyX86InstComments()
119 DecodePSHUFLWMask(MVT::v8i16, in EmitAnyX86InstComments()
128 DecodePSHUFLWMask(MVT::v16i16, in EmitAnyX86InstComments()
138 DecodeUNPCKHMask(MVT::v16i8, ShuffleMask); in EmitAnyX86InstComments()
146 DecodeUNPCKHMask(MVT::v16i8, ShuffleMask); in EmitAnyX86InstComments()
154 DecodeUNPCKHMask(MVT::v32i8, ShuffleMask); in EmitAnyX86InstComments()
161 DecodeUNPCKHMask(MVT::v8i16, ShuffleMask); in EmitAnyX86InstComments()
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/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp84 return CurDAG->getTargetConstant(Imm, MVT::i32); in getI32Imm()
286 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { in isInt32Immediate()
404 MVT::i32); in SelectImmShifterOperand()
431 MVT::i32); in SelectRegShifterOperand()
448 OffImm = CurDAG->getTargetConstant(0, MVT::i32); in SelectAddrModeImm12()
458 OffImm = CurDAG->getTargetConstant(0, MVT::i32); in SelectAddrModeImm12()
473 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); in SelectAddrModeImm12()
480 OffImm = CurDAG->getTargetConstant(0, MVT::i32); in SelectAddrModeImm12()
505 MVT::i32); in SelectLdStSOReg()
575 MVT::i32); in SelectLdStSOReg()
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DARMCallingConv.h28 static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in f64AssignAPCS()
58 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in CC_ARM_APCS_Custom_f64()
64 if (LocVT == MVT::v2f64 && in CC_ARM_APCS_Custom_f64()
71 static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in f64AssignAAPCS()
106 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in CC_ARM_AAPCS_Custom_f64()
112 if (LocVT == MVT::v2f64 && in CC_ARM_AAPCS_Custom_f64()
118 static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in f64RetAssign()
138 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in RetCC_ARM_APCS_Custom_f64()
144 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) in RetCC_ARM_APCS_Custom_f64()
149 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in RetCC_ARM_AAPCS_Custom_f64()
DARMSelectionDAGInfo.cpp52 EVT VT = MVT::i32; in EmitTargetCodeForMemcpy()
67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, in EmitTargetCodeForMemcpy()
68 DAG.getConstant(SrcOff, MVT::i32)), in EmitTargetCodeForMemcpy()
74 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); in EmitTargetCodeForMemcpy()
79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, in EmitTargetCodeForMemcpy()
80 DAG.getConstant(DstOff, MVT::i32)), in EmitTargetCodeForMemcpy()
85 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); in EmitTargetCodeForMemcpy()
98 VT = MVT::i16; in EmitTargetCodeForMemcpy()
101 VT = MVT::i8; in EmitTargetCodeForMemcpy()
106 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, in EmitTargetCodeForMemcpy()
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DARMISelLowering.cpp93 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, in addTypeForNEON()
94 MVT PromotedBitwiseVT) { in addTypeForNEON()
103 MVT ElemTy = VT.getVectorElementType(); in addTypeForNEON()
104 if (ElemTy != MVT::i64 && ElemTy != MVT::f64) in addTypeForNEON()
108 if (ElemTy == MVT::i32) { in addTypeForNEON()
151 void ARMTargetLowering::addDRTypeForNEON(MVT VT) { in addDRTypeForNEON()
153 addTypeForNEON(VT, MVT::f64, MVT::v2i32); in addDRTypeForNEON()
156 void ARMTargetLowering::addQRTypeForNEON(MVT VT) { in addQRTypeForNEON()
158 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); in addQRTypeForNEON()
430 addRegisterClass(MVT::i32, &ARM::tGPRRegClass); in ARMTargetLowering()
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