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Searched refs:SETLT (Results 1 – 23 of 23) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h747 SETLT, // 1 X 1 0 0 True if less than enumerator
758 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td43 IntRegs:$fval, SETLT)),
113 DoubleRegs:$fval, SETLT)),
DHexagonISelDAGToDAG.cpp833 if (cast<CondCodeSDNode>(N02)->get() == ISD::SETLT) { in SelectSelect()
/external/llvm/lib/CodeGen/
DAnalysis.cpp178 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
197 case ICmpInst::ICMP_SLT: return ISD::SETLT; in getICmpCondCode()
/external/llvm/lib/Target/MBlaze/
DMBlazeInstrInfo.td769 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETLT),
794 def : Pat<(setcc (i32 0), (i32 GPR:$R), SETLT),
822 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLT),
859 (i32 GPR:$T), (i32 GPR:$F), SETLT),
890 (i32 GPR:$T), (i32 GPR:$F), SETLT),
921 (i32 GPR:$T), (i32 GPR:$F), SETLT),
957 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETLT), bb:$T),
978 def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETLT), bb:$T),
999 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETLT), bb:$T),
DMBlazeInstrFPU.td160 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLT),
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp573 case ISD::SETLT: return PPC::PRED_LT; in getPredicateForSetCC()
600 case ISD::SETLT: return 0; // Bit #0 = SETOLT in getCRIdxForSetCC()
652 case ISD::SETLT: { in SelectSETCC()
685 case ISD::SETLT: { in SelectSETCC()
DPPCISelLowering.cpp1432 DAG.getConstant(8, MVT::i32), ISD::SETLT); in LowerVAARG()
3730 case ISD::SETLT: in LowerSELECT_CC()
3752 case ISD::SETLT: in LowerSELECT_CC()
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp503 CCs[RTLIB::OLT_F32] = ISD::SETLT; in InitCmpLibcallCCs()
504 CCs[RTLIB::OLT_F64] = ISD::SETLT; in InitCmpLibcallCCs()
2089 case ISD::SETLT: in SimplifySetCC()
2249 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); in SimplifySetCC()
2252 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) in SimplifySetCC()
2265 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) in SimplifySetCC()
2269 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) in SimplifySetCC()
2287 ISD::SETLT); in SimplifySetCC()
2626 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X in SimplifySetCC()
DSelectionDAGDumper.cpp307 case ISD::SETLT: return "setlt"; in getOperationName()
DLegalizeIntegerTypes.cpp831 case ISD::SETLT: in PromoteSetCCOperands()
2514 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 in IntegerExpandSetCCOperands()
2525 case ISD::SETLT: in IntegerExpandSetCCOperands()
2562 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || in IntegerExpandSetCCOperands()
2807 ISD::SETLT); in ExpandIntOp_UINT_TO_FP()
DLegalizeDAG.cpp1531 ISD::SETLT); in ExpandFCOPYSIGN()
1597 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; in LegalizeSetCCCondCode()
1603 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; in LegalizeSetCCCondCode()
2154 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT); in ExpandLegalINT_TO_FP()
2193 ISD::SETLT); in ExpandLegalINT_TO_FP()
2753 Tmp1, ISD::SETLT); in ExpandNode()
DLegalizeFloatTypes.cpp635 case ISD::SETLT: in SoftenSetCCOperands()
1231 Lo, Hi, DAG.getCondCode(ISD::SETLT)); in ExpandFloatRes_XINT_TO_FP()
DSelectionDAG.cpp274 case ISD::SETLT: in isSignedOp()
1603 case ISD::SETLT: return getConstant(C1.slt(C2), VT); in FoldSetCC()
1628 case ISD::SETLT: if (R==APFloat::cmpUnordered) in FoldSetCC()
DDAGCombiner.cpp3073 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { in visitOR()
8668 if ((CC == ISD::SETLT || CC == ISD::SETLE) && in SimplifySelectCC()
8729 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && in SimplifySelectCC()
8894 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || in SimplifySelectCC()
8895 (N1C->isOne() && CC == ISD::SETLT)) && in SimplifySelectCC()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp654 case ISD::SETLT: return SPCC::ICC_L; in IntCondCCodeToICC()
674 case ISD::SETLT: in FPCondCCodeToFCC()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td505 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
863 (setcc node:$lhs, node:$rhs, SETLT)>;
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp728 case ISD::SETLT: in EmitCMP()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp3079 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { in TranslateX86CC()
3083 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { in TranslateX86CC()
3095 case ISD::SETLT: return X86::COND_L; in TranslateX86CC()
3142 case ISD::SETLT: return X86::COND_B; in TranslateX86CC()
8047 ISD::SETLT); in LowerUINT_TO_FP()
8789 case ISD::SETLT: in LowerVSETCC()
8845 case ISD::SETLT: Swap = true; in LowerVSETCC()
9694 CC = ISD::SETLT; in LowerINTRINSIC_WO_CHAIN()
9724 CC = ISD::SETLT; in LowerINTRINSIC_WO_CHAIN()
13860 case ISD::SETLT: in PerformSELECTCombine()
[all …]
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp1094 case ISD::SETLT: return ARMCC::LT; in IntCCToARMCC()
1123 case ISD::SETLT: in FPCCToARMCC()
2768 case ISD::SETLT: in getARMCmp()
2771 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; in getARMCmp()
2785 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; in getARMCmp()
3598 case ISD::SETLT: Swap = true; // Fallthrough in LowerVSETCC()
3634 case ISD::SETLT: Swap = true; in LowerVSETCC()
8850 case ISD::SETLT: in PerformSELECT_CCCombine()
/external/llvm/lib/Target/NVPTX/
DNVPTXVector.td986 (setcc node:$lhs, node:$rhs, SETLT)>;
/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp2604 compareOp = ISD::SETLT; break; in LowerSETCC()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp541 case ISD::SETLT: in FPCondCCodeToFCC()