Searched refs:SETOEQ (Results 1 – 18 of 18) sorted by relevance
/external/llvm/lib/CodeGen/ |
D | Analysis.cpp | 155 case FCmpInst::FCMP_OEQ: return ISD::SETOEQ; in getFCmpCondCode() 176 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
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/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 727 SETOEQ, // 0 0 0 1 True if ordered and equal enumerator
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/external/llvm/lib/Target/CellSPU/ |
D | README.txt | 81 SETOEQ unimplemented
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D | SPUISelLowering.cpp | 2593 case ISD::SETOEQ: in LowerSETCC()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonISelLowering.cpp | 1110 setCondCodeAction(ISD::SETOEQ, MVT::f32, Legal); in HexagonTargetLowering() 1111 setCondCodeAction(ISD::SETOEQ, MVT::f64, Legal); in HexagonTargetLowering() 1203 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); in HexagonTargetLowering() 1206 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); in HexagonTargetLowering()
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/external/llvm/lib/Target/MBlaze/ |
D | MBlazeInstrFPU.td | 146 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOEQ),
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGDumper.cpp | 288 case ISD::SETOEQ: return "setoeq"; in getOperationName()
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D | LegalizeFloatTypes.cpp | 624 case ISD::SETOEQ: in SoftenSetCCOperands() 1310 LHSHi, RHSHi, ISD::SETOEQ); in FloatExpandSetCCOperands()
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D | TargetLowering.cpp | 2410 if (Cond == ISD::SETOEQ && in SimplifySetCC() 2423 if (Cond == ISD::SETOEQ && in SimplifySetCC()
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D | SelectionDAG.cpp | 327 case ISD::SETOEQ: // SETEQ & SETU[LG]E in getSetCCAndOperation() 1576 case ISD::SETOEQ: in FoldSetCC() 1622 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); in FoldSetCC()
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D | LegalizeDAG.cpp | 1594 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; in LegalizeSetCCCondCode()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelDAGToDAG.cpp | 568 case ISD::SETOEQ: in getPredicateForSetCC() 603 case ISD::SETOEQ: in getCRIdxForSetCC()
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/external/llvm/include/llvm/Target/ |
D | TargetSelectionDAG.td | 498 def SETOEQ : CondCode; def SETOGT : CondCode; 829 (setcc node:$lhs, node:$rhs, SETOEQ)>;
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/external/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 671 case ISD::SETOEQ: return SPCC::FCC_E; in FPCondCCodeToFCC()
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 241 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); in X86TargetLowering() 242 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); in X86TargetLowering() 243 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); in X86TargetLowering() 3150 case ISD::SETOEQ: in TranslateX86CC() 8785 case ISD::SETOEQ: in LowerVSETCC() 9307 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { in LowerBRCOND()
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/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 1110 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; in FPCCToARMCC() 3021 if (CC == ISD::SETOEQ) in OptimizeVFPBrcond() 3074 (CC == ISD::SETEQ || CC == ISD::SETOEQ || in LowerBR_CC() 3595 case ISD::SETOEQ: in LowerVSETCC()
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/external/llvm/lib/Target/NVPTX/ |
D | NVPTXVector.td | 952 (setcc node:$lhs, node:$rhs, SETOEQ)>;
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/external/llvm/lib/Target/Mips/ |
D | MipsISelLowering.cpp | 539 case ISD::SETOEQ: return Mips::FCOND_OEQ; in FPCondCCodeToFCC()
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