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Searched refs:SimpleTy (Results 1 – 25 of 30) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DValueTypes.h144 SimpleValueType SimpleTy; variable
146 MVT() : SimpleTy((SimpleValueType)(INVALID_SIMPLE_VALUE_TYPE)) {} in MVT()
147 MVT(SimpleValueType SVT) : SimpleTy(SVT) { } in MVT()
149 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
150 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
151 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
152 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
153 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
154 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
158 return ((SimpleTy >= MVT::FIRST_FP_VALUETYPE && in isFloatingPoint()
[all …]
/external/llvm/include/llvm/Target/
DTargetLowering.h224 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; in getRegClassFor()
236 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy]; in getRepRegClassFor()
244 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy]; in getRepRegClassCostFor()
252 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); in isTypeLegal()
253 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; in isTypeLegal()
267 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy]; in getTypeAction()
271 unsigned I = VT.getSimpleVT().SimpleTy; in setTypeAction()
393 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; in getOperationAction()
421 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; in getLoadExtAction()
438 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy] in getTruncStoreAction()
[all …]
/external/llvm/lib/VMCore/
DValueTypes.cpp99 switch (V.SimpleTy) { in getEVTString()
156 switch (V.SimpleTy) { in getTypeForEVT()
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp1529 switch (NVT.getSimpleVT().SimpleTy) { in SelectAtomicLoadAdd()
1741 switch (NVT.getSimpleVT().SimpleTy) { in SelectAtomicLoadArith()
2141 switch (NVT.getSimpleVT().SimpleTy) { in Select()
2178 switch (NVT.getSimpleVT().SimpleTy) { in Select()
2206 switch (NVT.getSimpleVT().SimpleTy) { in Select()
2214 switch (NVT.getSimpleVT().SimpleTy) { in Select()
2224 switch (NVT.getSimpleVT().SimpleTy) { in Select()
2306 switch (NVT.getSimpleVT().SimpleTy) { in Select()
2314 switch (NVT.getSimpleVT().SimpleTy) { in Select()
2325 switch (NVT.getSimpleVT().SimpleTy) { in Select()
[all …]
DX86FastISel.cpp183 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitLoad()
240 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
292 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
845 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpOpcode()
862 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpImmediateOpcode()
1104 switch (SourceVT.SimpleTy) { in X86SelectBranch()
2026 switch (VT.SimpleTy) { in TargetMaterializeConstant()
2148 switch (VT.SimpleTy) { in TargetMaterializeFloatZero()
DX86RegisterInfo.cpp594 switch (VT.getSimpleVT().SimpleTy) { in getX86SubSuperRegister()
DX86ISelLowering.cpp1425 switch (VT.getSimpleVT().SimpleTy) { in findRepresentativeClass()
5599 switch (VT.SimpleTy) { in LowerVECTOR_SHUFFLEtoBlend()
6085 switch (VT.SimpleTy) { in RewriteAsNarrowerShuffle()
8106 switch (DstTy.getSimpleVT().SimpleTy) { in FP_TO_INTHelper()
11000 switch (VT.getSimpleVT().SimpleTy) { in LowerSIGN_EXTEND_INREG()
11129 switch(T.getSimpleVT().SimpleTy) { in LowerCMP_SWAP()
14629 switch (VT.getSimpleVT().SimpleTy) { in PerformShiftCombine()
14640 switch (VT.getSimpleVT().SimpleTy) { in PerformShiftCombine()
14649 switch (VT.getSimpleVT().SimpleTy) { in PerformShiftCombine()
16720 switch (VT.getSimpleVT().SimpleTy) { in getRegForInlineAsmConstraint()
/external/llvm/lib/Target/MSP430/
DMSP430ISelDAGToDAG.cpp309 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad()
337 switch (VT.SimpleTy) { in SelectIndexedLoad()
DMSP430ISelLowering.cpp328 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
333 << RegVT.getSimpleVT().SimpleTy << "\n"; in LowerCCCArguments()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp266 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); in ExpandConstantFP()
1904 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in ExpandFPLibCall()
1921 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in ExpandIntLibCall()
1936 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in isDivRemLibcallAvailable()
1983 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in ExpandDivRemLibCall()
2202 switch (Op0.getValueType().getSimpleVT().SimpleTy) { in ExpandLegalINT_TO_FP()
2251 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); in PromoteLegalINT_TO_FP()
2293 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); in PromoteLegalFP_TO_INT()
2324 switch (VT.getSimpleVT().SimpleTy) { in ExpandBSWAP()
2482 switch (VT.SimpleTy) { in ExpandAtomic()
[all …]
DLegalizeIntegerTypes.cpp1179 switch (VT.SimpleTy) { in ExpandAtomic()
1188 switch (VT.SimpleTy) { in ExpandAtomic()
1197 switch (VT.SimpleTy) { in ExpandAtomic()
1206 switch (VT.SimpleTy) { in ExpandAtomic()
1215 switch (VT.SimpleTy) { in ExpandAtomic()
1224 switch (VT.SimpleTy) { in ExpandAtomic()
1233 switch (VT.SimpleTy) { in ExpandAtomic()
1242 switch (VT.SimpleTy) { in ExpandAtomic()
2757 switch (VT.getSimpleVT().SimpleTy) { in EVTToAPFloatSemantics()
DSelectionDAG.cpp63 switch (VT.getSimpleVT().SimpleTy) { in EVTToAPFloatSemantics()
692 Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != 0; in RemoveNodeFromCSEMaps()
693 ValueTypeNodes[VT.getSimpleVT().SimpleTy] = 0; in RemoveNodeFromCSEMaps()
1255 if (VT.isSimple() && (unsigned)VT.getSimpleVT().SimpleTy >= in getValueType()
1257 ValueTypeNodes.resize(VT.getSimpleVT().SimpleTy+1); in getValueType()
1260 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT().SimpleTy]; in getValueType()
3465 LVT = (MVT::SimpleValueType)(LVT.SimpleTy - 1); in FindOptimalMemOpLowering()
3480 VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1); in FindOptimalMemOpLowering()
3485 VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1); in FindOptimalMemOpLowering()
5832 return &SimpleVTArray->VTs[VT.getSimpleVT().SimpleTy]; in getValueTypeList()
DTargetLowering.cpp711 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; in findRepresentativeClass()
903 return PointerTy.SimpleTy; in getSetCCResultType()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp910 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
922 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
944 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
957 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
DPPCISelLowering.cpp1794 switch (ValVT.getSimpleVT().SimpleTy) { in LowerFormalArguments_SVR4()
2018 switch(ObjectVT.getSimpleVT().SimpleTy) { in LowerFormalArguments_Darwin()
2135 switch (ObjectVT.getSimpleVT().SimpleTy) { in LowerFormalArguments_Darwin()
3362 switch (Arg.getValueType().getSimpleVT().SimpleTy) { in LowerCall_Darwin()
3788 switch (Op.getValueType().getSimpleVT().SimpleTy) { in LowerFP_TO_INT()
5963 switch (VT.getSimpleVT().SimpleTy) { in isFMAFasterThanMulAndAdd()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp896 switch (VT.getSimpleVT().SimpleTy) { in ARMSimplifyAddress()
952 if (VT.getSimpleVT().SimpleTy == MVT::f32 || in AddLoadStoreOperands()
953 VT.getSimpleVT().SimpleTy == MVT::f64) in AddLoadStoreOperands()
1003 switch (VT.getSimpleVT().SimpleTy) { in ARMEmitLoad()
1118 switch (VT.getSimpleVT().SimpleTy) { in ARMEmitStore()
1419 switch (SrcVT.getSimpleVT().SimpleTy) { in ARMEmitCmp()
1903 switch (static_cast<EVT>(ArgVT).getSimpleVT().SimpleTy) { in ProcessCallArgs()
2557 switch (SrcVT.getSimpleVT().SimpleTy) { in ARMEmitIntExt()
DARMISelDAGToDAG.cpp1408 switch (LoadedVT.getSimpleVT().SimpleTy) { in SelectT2IndexedLoad()
1609 switch (VT.getSimpleVT().SimpleTy) { in SelectVLD()
1746 switch (VT.getSimpleVT().SimpleTy) { in SelectVST()
1908 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDSTLane()
2022 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDDup()
2348 switch (VT.getSimpleVT().SimpleTy) { in SelectCMOVOp()
2727 switch (VT.getSimpleVT().SimpleTy) { in Select()
2747 switch (VT.getSimpleVT().SimpleTy) { in Select()
2767 switch (VT.getSimpleVT().SimpleTy) { in Select()
DARMISelLowering.cpp846 switch (VT.getSimpleVT().SimpleTy) { in findRepresentativeClass()
7234 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { in AddCombineToVPADDL()
9031 switch (VT.getSimpleVT().SimpleTy) { in allowsUnalignedMemoryAccesses()
9084 switch (VT.getSimpleVT().SimpleTy) { in isLegalT1AddressImmediate()
9114 switch (VT.getSimpleVT().SimpleTy) { in isLegalT2AddressImmediate()
9155 switch (VT.getSimpleVT().SimpleTy) { in isLegalAddressImmediate()
9182 switch (VT.getSimpleVT().SimpleTy) { in isLegalT2ScaledAddressingMode()
9240 switch (VT.getSimpleVT().SimpleTy) { in isLegalAddressingMode()
/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp520 switch(VT.getSimpleVT().SimpleTy){ in getSetCCResultType()
1152 switch (ObjectVT.getSimpleVT().SimpleTy) { in LowerFormalArguments()
1324 switch (Arg.getValueType().getSimpleVT().SimpleTy) { in LowerCall()
1680 switch (VT.getSimpleVT().SimpleTy) { in LowerBUILD_VECTOR()
1971 switch (Op.getValueType().getSimpleVT().SimpleTy) { in LowerSCALAR_TO_VECTOR()
1990 switch (Op0.getValueType().getSimpleVT().SimpleTy) { in LowerSCALAR_TO_VECTOR()
2033 switch (VT.getSimpleVT().SimpleTy) { in LowerEXTRACT_VECTOR_ELT()
2124 switch (VT.getSimpleVT().SimpleTy) { in LowerEXTRACT_VECTOR_ELT()
2361 switch (VT.getSimpleVT().SimpleTy) { in LowerCTPOP()
DSPUISelDAGToDAG.cpp575 switch( VT.SimpleTy ) { in getRC()
649 switch (Op0VT.getSimpleVT().SimpleTy) { in Select()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp207 MVT::SimpleValueType TargetVT = LD->getValueType(0).getSimpleVT().SimpleTy; in SelectLoad()
393 N1.getNode()->getValueType(0).getSimpleVT().SimpleTy; in SelectStore()
/external/llvm/utils/TableGen/
DIntrinsicEmitter.cpp340 getSimpleVT().SimpleTy, Sig); in EncodeFixedType()
DCodeGenDAGPatterns.cpp517 VTOperand.MergeInTypeInfo(IVT.getSimpleVT().SimpleTy, TP); in EnforceVectorEltTypeIs()
532 if (EVT(TypeVec[i]).getVectorElementType().getSimpleVT().SimpleTy != VT) { in EnforceVectorEltTypeIs()
561 EEVT::TypeSet EltTypeSet(IVT.getSimpleVT().SimpleTy, TP); in EnforceVectorSubVectorTypeIs()
567 EEVT::TypeSet EltTypeSet(IVT.getSimpleVT().SimpleTy, TP); in EnforceVectorSubVectorTypeIs()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1120 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
1125 << RegVT.getSimpleVT().SimpleTy << "\n"; in LowerCCCArguments()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1523 switch (VT.getSimpleVT().SimpleTy) { in getRegForInlineAsmConstraint()

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