/external/llvm/lib/CodeGen/ |
D | LiveIntervalUnion.h | 120 Query(LiveInterval *VReg, LiveIntervalUnion *LIU): in Query() argument 121 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false), in Query() 136 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) { in init() argument 137 assert(VReg && LIU && "Invalid arguments"); in init() 138 if (UserTag == UTag && VirtReg == VReg && in init() 145 VirtReg = VReg; in init() 163 bool isSeenInterference(LiveInterval *VReg) const;
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D | LiveIntervalUnion.cpp | 151 LiveInterval *VReg = LiveUnionI.value(); in collectInterferingVRegs() local 152 if (VReg != RecentReg && !isSeenInterference(VReg)) { in collectInterferingVRegs() 153 RecentReg = VReg; in collectInterferingVRegs() 154 InterferingVRegs.push_back(VReg); in collectInterferingVRegs()
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D | MachineFunction.cpp | 409 unsigned VReg = MRI.getLiveInVirtReg(PReg); in addLiveIn() local 410 if (VReg) { in addLiveIn() 411 assert(MRI.getRegClass(VReg) == RC && "Register class mismatch!"); in addLiveIn() 412 return VReg; in addLiveIn() 414 VReg = MRI.createVirtualRegister(RC); in addLiveIn() 415 MRI.addLiveIn(PReg, VReg); in addLiveIn() 416 return VReg; in addLiveIn()
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D | LiveRangeEdit.cpp | 35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createFrom() local 38 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createFrom() 40 LiveInterval &LI = LIS.getOrCreateInterval(VReg); in createFrom()
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D | TailDuplication.cpp | 231 unsigned VReg = SSAUpdateVRs[i]; in TailDuplicateAndUpdate() local 232 SSAUpdate.Initialize(VReg); in TailDuplicateAndUpdate() 236 MachineInstr *DefMI = MRI->getVRegDef(VReg); in TailDuplicateAndUpdate() 240 SSAUpdate.AddAvailableValue(DefBB, VReg); in TailDuplicateAndUpdate() 245 SSAUpdateVals.find(VReg); in TailDuplicateAndUpdate() 253 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg); in TailDuplicateAndUpdate()
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D | MachineRegisterInfo.cpp | 252 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { in getLiveInPhysReg() 254 if (I->second == VReg) in getLiveInPhysReg()
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D | RegAllocFast.cpp | 169 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | InstrEmitter.cpp | 271 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); in getVR() local 274 if (!VReg) { in getVR() 276 VReg = MRI->createVirtualRegister(RC); in getVR() 279 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR() 280 return VReg; in getVR() 302 unsigned VReg = getVR(Op, VRBaseMap); in AddRegisterOperand() local 303 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); in AddRegisterOperand() 319 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { in AddRegisterOperand() 322 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddRegisterOperand() 323 VReg = NewVReg; in AddRegisterOperand() [all …]
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D | InstrEmitter.h | 83 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
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/external/llvm/lib/Target/ARM/ |
D | Thumb1RegisterInfo.cpp | 599 unsigned VReg = 0; in eliminateFrameIndex() local 697 VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass); in eliminateFrameIndex() 702 emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg, in eliminateFrameIndex() 705 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset); in eliminateFrameIndex() 709 emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII, in eliminateFrameIndex() 712 MI.getOperand(i).ChangeToRegister(VReg, false, false, true); in eliminateFrameIndex()
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D | ARMISelLowering.cpp | 2571 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); in VarArgStyleRegisters() local 2572 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in VarArgStyleRegisters()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 1905 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); in LowerFormalArguments_SVR4() local 1906 if (!VReg) in LowerFormalArguments_SVR4() 1907 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); in LowerFormalArguments_SVR4() 1909 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); in LowerFormalArguments_SVR4() 1924 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); in LowerFormalArguments_SVR4() local 1925 if (!VReg) in LowerFormalArguments_SVR4() 1926 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); in LowerFormalArguments_SVR4() 1928 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); in LowerFormalArguments_SVR4() 2090 unsigned VReg; in LowerFormalArguments_Darwin() local 2092 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_Darwin() [all …]
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/external/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 211 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments() local 212 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments() 213 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in LowerFormalArguments() 323 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments() local 324 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); in LowerFormalArguments() 325 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); in LowerFormalArguments()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonISelLowering.cpp | 848 unsigned VReg = in LowerFormalArguments() local 850 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments() 851 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments() 853 unsigned VReg = in LowerFormalArguments() local 855 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments() 856 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
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/external/llvm/lib/Target/CellSPU/ |
D | SPUISelLowering.cpp | 638 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); in LowerLOAD() local 649 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); in LowerLOAD() 650 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); in LowerLOAD() 833 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); in LowerSTORE() local 844 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); in LowerSTORE() 845 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); in LowerSTORE() 1187 unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass); in LowerFormalArguments() local 1188 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments() 1189 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); in LowerFormalArguments() 1235 unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::VECREGRegClass); in LowerFormalArguments() local [all …]
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/external/llvm/lib/Target/XCore/ |
D | XCoreISelLowering.cpp | 1130 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); in LowerCCCArguments() local 1131 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments() 1132 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerCCCArguments() 1180 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); in LowerCCCArguments() local 1181 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments() 1182 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in LowerCCCArguments()
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/external/llvm/include/llvm/CodeGen/ |
D | MachineRegisterInfo.h | 459 unsigned getLiveInPhysReg(unsigned VReg) const;
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/external/llvm/lib/Target/MSP430/ |
D | MSP430ISelLowering.cpp | 338 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass); in LowerCCCArguments() local 339 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments() 340 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
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/external/llvm/lib/Target/Mips/ |
D | MipsISelLowering.cpp | 829 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); in AddLiveIn() local 830 MF.getRegInfo().addLiveIn(PReg, VReg); in AddLiveIn() 831 return VReg; in AddLiveIn() 2959 unsigned VReg = AddLiveIn(MF, *Reg, &Mips::CPU64RegsRegClass); in CopyMips64ByValRegs() local 2962 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64), in CopyMips64ByValRegs()
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/external/webkit/Source/JavaScriptCore/jit/ |
D | JIT.h | 536 void emitJumpSlowCaseIfNotJSCell(RegisterID, int VReg);
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 2048 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], in LowerFormalArguments() local 2050 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments() 2075 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], in LowerFormalArguments() local 2077 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); in LowerFormalArguments()
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