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Searched refs:getKillRegState (Results 1 – 25 of 31) sorted by relevance

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/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp43 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
47 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
51 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
55 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
59 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
63 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
67 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
71 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
75 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
79 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp184 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstruction()
185 .addReg(Reg1, getKillRegState(Reg1IsKill)) in commuteInstruction()
436 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
438 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
453 getKillRegState(isKill)), in StoreRegToStackSlot()
462 getKillRegState(isKill)), in StoreRegToStackSlot()
469 getKillRegState(isKill)), in StoreRegToStackSlot()
478 getKillRegState(isKill)), in StoreRegToStackSlot()
484 getKillRegState(isKill)), in StoreRegToStackSlot()
489 getKillRegState(isKill)), in StoreRegToStackSlot()
[all …]
DPPCRegisterInfo.cpp418 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); in lowerCRSpilling()
431 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), in lowerCRSpilling()
/external/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp228 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction()
229 .addReg(Src2Reg, getKillRegState(Src2Kill)); in ExpandFPMLxInstruction()
239 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
240 .addReg(AccReg, getKillRegState(AccKill)); in ExpandFPMLxInstruction()
242 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
DThumb1InstrInfo.cpp46 .addReg(SrcReg, getKillRegState(KillSrc))); in copyPhysReg()
74 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
DARMLoadStoreOptimizer.cpp339 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset) in MergeOps()
350 .addReg(Base, getKillRegState(BaseKill)) in MergeOps()
354 | getKillRegState(Regs[i].second)); in MergeOps()
779 .addReg(Base, getKillRegState(BaseKill)) in MergeBaseUpdateLSMultiple()
932 .addReg(Base, getKillRegState(isLd ? BaseKill : false)) in MergeBaseUpdateLoadStore()
935 getKillRegState(MO.isKill()))); in MergeBaseUpdateLoadStore()
966 .addReg(MO.getReg(), getKillRegState(MO.isKill())) in MergeBaseUpdateLoadStore()
972 .addReg(MO.getReg(), getKillRegState(MO.isKill())) in MergeBaseUpdateLoadStore()
1085 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1090 .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef)) in InsertLDR_STR()
[all …]
DARMBaseInstrInfo.cpp655 .addReg(SrcReg, getKillRegState(KillSrc)))); in copyPhysReg()
676 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
678 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
775 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
779 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
787 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
798 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
802 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
815 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
822 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
[all …]
DARMExpandPseudoInsts.cpp548 getKillRegState(MO.isKill())); in ExpandLaneOp()
696 getKillRegState(MI.getOperand(2).isKill())) in ExpandMI()
709 getKillRegState(MI.getOperand(2).isKill())) in ExpandMI()
721 getKillRegState(MI.getOperand(2).isKill())) in ExpandMI()
735 getKillRegState(MI.getOperand(2).isKill())) in ExpandMI()
737 getKillRegState(MI.getOperand(3).isKill())) in ExpandMI()
DThumb2InstrInfo.cpp121 .addReg(SrcReg, getKillRegState(KillSrc))); in copyPhysReg()
143 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
DThumb1FrameLowering.cpp323 MIB.addReg(Reg, getKillRegState(isKill)); in spillCalleeSavedRegisters()
DARMFrameLowering.cpp630 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); in emitPushInst()
634 .addReg(Regs[0].first, getKillRegState(Regs[0].second)) in emitPushInst()
DThumb1RegisterInfo.cpp272 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal); in emitThumbRegPlusImmediate()
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp286 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
289 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
292 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
308 .addReg(SrcReg, getKillRegState(isKill)); in storeRegToStackSlot()
311 .addReg(SrcReg, getKillRegState(isKill)); in storeRegToStackSlot()
314 .addReg(SrcReg, getKillRegState(isKill)); in storeRegToStackSlot()
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
57 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
101 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp343 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
355 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
371 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
DXCoreRegisterInfo.cpp235 .addReg(Reg, getKillRegState(isKill)) in eliminateFrameIndex()
256 .addReg(Reg, getKillRegState(isKill)) in eliminateFrameIndex()
285 .addReg(Reg, getKillRegState(isKill)) in eliminateFrameIndex()
/external/llvm/lib/Target/Hexagon/
DHexagonNewValueJump.cpp612 .addReg(cmpReg1, getKillRegState(MO1IsKill)) in runOnMachineFunction()
613 .addReg(cmpOp2, getKillRegState(MO2IsKill)) in runOnMachineFunction()
619 .addReg(cmpReg1, getKillRegState(MO1IsKill)) in runOnMachineFunction()
DHexagonInstrInfo.cpp372 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
376 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
380 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
/external/llvm/lib/Target/Mips/
DMips16InstrInfo.cpp79 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
DMipsSEInstrInfo.cpp151 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
177 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/external/llvm/lib/Target/MBlaze/
DMBlazeInstrInfo.cpp89 .addReg(SrcReg, getKillRegState(KillSrc)).addReg(MBlaze::R0); in copyPhysReg()
98 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill)) in storeRegToStackSlot()
/external/llvm/lib/Target/CellSPU/
DSPUInstrInfo.cpp135 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
168 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx); in storeRegToStackSlot()
/external/llvm/lib/CodeGen/
DMachineInstrBundle.cpp199 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()
/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h312 inline unsigned getKillRegState(bool B) { in getKillRegState() function

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