| /external/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 26 CCState::CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &mf, in CCState() function in CCState
42 void CCState::HandleByVal(unsigned ValNo, MVT ValVT, in HandleByVal()
59 void CCState::MarkAllocated(unsigned Reg) { in MarkAllocated()
67 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeFormalArguments()
86 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in CheckReturn()
100 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn()
118 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands()
136 void CCState::AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs, in AnalyzeCallOperands()
155 void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeCallResult()
172 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { in AnalyzeCallResult()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.h | 30 CCState &State, bool CanFail) { in f64AssignAPCS()
61 CCState &State) { in CC_ARM_APCS_Custom_f64()
73 CCState &State, bool CanFail) { in f64AssignAAPCS()
109 CCState &State) { in CC_ARM_AAPCS_Custom_f64()
119 CCValAssign::LocInfo &LocInfo, CCState &State) { in f64RetAssign()
141 CCState &State) { in RetCC_ARM_APCS_Custom_f64()
152 CCState &State) { in RetCC_ARM_AAPCS_Custom_f64()
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| D | ARMISelLowering.h | 476 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
484 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
492 virtual void HandleByVal(CCState *, unsigned &, unsigned) const;
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| D | ARMFastISel.cpp | 1909 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, *Context); in ProcessCallArgs()
2053 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context); in FinishCall()
2113 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext()); in SelectRet()
2213 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context); in ARMEmitLibcall()
2324 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context); in SelectCall()
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| D | ARMISelLowering.cpp | 74 class ARMCCState : public CCState {
79 : CCState(CC, isVarArg, MF, TM, locs, C) { in ARMCCState()
1708 CCState *State, unsigned &size, unsigned Align) const { in HandleByVal()
1932 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); in CanLowerReturn()
2580 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF, in computeRegArea()
2607 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, in VarArgStyleRegisters()
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 28 class CCState; variable
137 ISD::ArgFlagsTy ArgFlags, CCState &State);
144 ISD::ArgFlagsTy &ArgFlags, CCState &State);
154 class CCState {
173 CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 54 ISD::ArgFlagsTy ArgFlags, CCState &State);
59 ISD::ArgFlagsTy ArgFlags, CCState &State);
64 ISD::ArgFlagsTy ArgFlags, CCState &State);
69 ISD::ArgFlagsTy ArgFlags, CCState &State);
74 ISD::ArgFlagsTy ArgFlags, CCState &State);
79 ISD::ArgFlagsTy ArgFlags, CCState &State);
84 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon_VarArg()
133 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon()
171 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon32()
189 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon64()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 222 MipsCC(CallingConv::ID CallConv, bool IsO32, CCState &Info);
239 const CCState &getCCInfo() const { return CCInfo; } in getCCInfo()
292 CCState &CCInfo;
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| D | MipsISelLowering.cpp | 2423 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_MipsO32()
2603 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), in LowerCall()
2790 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), in LowerCallResult()
2837 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), in LowerFormalArguments()
2979 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), in CanLowerReturn()
2996 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs, in LowerReturn()
3375 CCState &Info) in MipsCC()
3723 const CCState &CCInfo = CC.getCCInfo(); in writeVarArgRegs()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 41 CCState &State);
661 CCState &State) { in CC_MBlaze_AssignReg()
712 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCall()
851 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCallResult()
894 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerFormalArguments()
1026 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerReturn()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.h | 42 void AnalyzeFormalArguments(CCState &State,
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| D | AMDGPUISelLowering.cpp | 72 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State, in AnalyzeFormalArguments()
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| D | SIISelLowering.cpp | 140 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerFormalArguments()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 146 void SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG,
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| D | AArch64ISelLowering.cpp | 800 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_AArch64NoMoreRegs()
823 AArch64TargetLowering::SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, in SaveVarArgRegisters()
904 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerFormalArguments()
1015 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerReturn()
1112 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), in LowerCall()
1350 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), in LowerCallResult()
1440 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(), in IsEligibleForTailCallOptimization()
1453 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), in IsEligibleForTailCallOptimization()
1458 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), in IsEligibleForTailCallOptimization()
1484 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(), in IsEligibleForTailCallOptimization()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 38 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_SRet()
51 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_f64()
92 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerReturn()
159 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerFormalArguments()
363 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCall()
594 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCall()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 324 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCCCArguments()
420 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerReturn()
470 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCCCCallTo()
607 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCallResult()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 939 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCCCCallTo()
1062 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCallResult()
1122 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCCCArguments()
1230 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); in CanLowerReturn()
1246 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerReturn()
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 42 class CCState; variable
1999 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {} in HandleByVal() argument
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 42 CCState &State);
47 CCState &State);
52 CCState &State);
1764 CCState &State) { in CC_PPC32_SVR4_Custom_Dummy()
1772 CCState &State) { in CC_PPC32_SVR4_Custom_AlignArgRegs()
1799 CCState &State) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
1916 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerFormalArguments_32SVR4()
1977 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerFormalArguments_32SVR4()
3283 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCallResult()
3485 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCall_32SVR4()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 751 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, in X86SelectRet()
1784 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, in DoSelectCall()
2010 CCState CCRetInfo(CC, false, *FuncInfo.MF, TM, RVLocs, in DoSelectCall()
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| D | X86ISelLowering.cpp | 1589 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), in CanLowerReturn()
1604 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), in LowerReturn()
1770 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCallResult()
1974 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), in LowerFormalArguments()
2320 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), in LowerCall()
2883 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), in IsEligibleForTailCallOptimization()
2904 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), in IsEligibleForTailCallOptimization()
2918 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), in IsEligibleForTailCallOptimization()
2923 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), in IsEligibleForTailCallOptimization()
2950 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), in IsEligibleForTailCallOptimization()
|