/external/llvm/utils/TableGen/ |
D | CodeGenInstruction.h | 101 DagInit *MIOperandInfo; member 112 MIOperandInfo(MIOI) {} in OperandInfo()
|
D | CodeGenInstruction.cpp | 184 DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo; in ParseOperandName() 578 DagInit *MIOI = ResultInst->Operands[i].MIOperandInfo; in CodeGenInstAlias() 597 DagInit *MIOI = ResultInst->Operands[i].MIOperandInfo; in CodeGenInstAlias()
|
D | InstrInfoEmitter.cpp | 85 DagInit *MIOI = Inst.Operands[i].MIOperandInfo; in GetOperandInfo()
|
D | AsmMatcherEmitter.cpp | 1000 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef(); in getOperandClass()
|
/external/llvm/lib/Target/ARM/ |
D | ARMInstrThumb.td | 136 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 152 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 160 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 168 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 180 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 192 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 204 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 218 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
|
D | ARMInstrInfo.td | 510 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 521 let MIOperandInfo = (ops GPR, i32imm); 532 let MIOperandInfo = (ops GPR, GPR, i32imm); 543 let MIOperandInfo = (ops GPR, i32imm); 754 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 766 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 778 let MIOperandInfo = (ops i32imm); 790 let MIOperandInfo = (ops i32imm); 805 let MIOperandInfo = (ops GPRnopc, i32imm); 820 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); [all …]
|
D | ARMInstrNEON.td | 65 let MIOperandInfo = (ops i32imm); 72 let MIOperandInfo = (ops i32imm); 79 let MIOperandInfo = (ops i32imm); 224 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 234 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 244 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 255 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 265 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); [all …]
|
D | ARMInstrThumb2.td | 52 let MIOperandInfo = (ops rGPR, i32imm); 157 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 187 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 198 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 209 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 227 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 246 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm); 257 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm); 265 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm); 271 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
|
/external/llvm/lib/Target/Hexagon/ |
D | HexagonOperands.td | 819 let MIOperandInfo = (ops IntRegs, IntRegs); 824 let MIOperandInfo = (ops IntRegs, IntRegs); 830 let MIOperandInfo = (ops IntRegs, s11Imm); 835 let MIOperandInfo = (ops IntRegs, s11Imm);
|
/external/llvm/lib/Target/X86/ |
D | X86InstrFragmentsSIMD.td | 231 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 237 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
|
D | X86InstrInfo.td | 323 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 358 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm); 361 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm); 364 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm); 367 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm); 375 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm); 389 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, 400 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 524 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm); 531 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
|
/external/llvm/lib/Target/Mips/ |
D | MipsInstrInfo.td | 256 let MIOperandInfo = (ops CPURegs, simm16); 263 let MIOperandInfo = (ops CPU64Regs, simm16_64); 270 let MIOperandInfo = (ops CPURegs, simm16); 276 let MIOperandInfo = (ops CPU64Regs, simm16_64);
|
D | Mips16InstrInfo.td | 24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16Regs); 30 let MIOperandInfo = (ops CPU16Regs, simm16);
|
/external/llvm/include/llvm/Target/ |
D | Target.td | 563 dag MIOperandInfo = (ops); 621 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and 626 let MIOperandInfo = OpTypes; 634 let MIOperandInfo = OpTypes;
|
/external/llvm/lib/Target/Sparc/ |
D | SparcInstrInfo.td | 72 let MIOperandInfo = (ops IntRegs, IntRegs); 76 let MIOperandInfo = (ops IntRegs, i32imm);
|
/external/llvm/lib/Target/R600/ |
D | R600Instructions.td | 58 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index); 63 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index); 95 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
|
/external/llvm/lib/Target/PowerPC/ |
D | PPCInstr64Bit.td | 33 let MIOperandInfo = (ops i32imm:$imm); 38 let MIOperandInfo = (ops symbolLo64:$off, ptr_rc:$reg);
|
D | PPCInstrInfo.td | 381 let MIOperandInfo = (ops symbolLo:$imm, ptr_rc:$reg); 386 let MIOperandInfo = (ops ptr_rc:$offreg, ptr_rc:$ptrreg); 390 let MIOperandInfo = (ops symbolLo:$imm, ptr_rc:$reg);
|
/external/llvm/lib/Target/MBlaze/ |
D | MBlazeInstrInfo.td | 103 let MIOperandInfo = (ops GPR, simm16); 109 let MIOperandInfo = (ops GPR, GPR);
|
/external/llvm/lib/Target/MSP430/ |
D | MSP430InstrInfo.td | 76 let MIOperandInfo = (ops GR16, i16imm); 81 let MIOperandInfo = (ops GR16, i16imm);
|
/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.td | 546 // InOperandList (expanded by ComplexPatterns and MIOperandInfo) was functional, 553 // the cmp/cmn aliases didn't use the MIOperandInfo to determine how operands 1140 // MIOperandInfo *might* have been able to do it, but at the cost of 3875 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift); 3943 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
|
/external/llvm/lib/Target/XCore/ |
D | XCoreInstrInfo.td | 186 let MIOperandInfo = (ops i32imm, i32imm);
|
/external/llvm/lib/Target/NVPTX/ |
D | NVPTXInstrInfo.td | 1223 let MIOperandInfo = (ops Int32Regs, i32imm); 1227 let MIOperandInfo = (ops Int64Regs, i64imm);
|
/external/llvm/docs/ |
D | WritingAnLLVMBackend.rst | 772 let MIOperandInfo = (ops IntRegs, IntRegs);
|