| /external/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 543 MachineOperand Op(MachineOperand::MO_Immediate); in CreateImm()
544 Op.setImm(Val); in CreateImm()
545 return Op; in CreateImm()
549 MachineOperand Op(MachineOperand::MO_CImmediate); in CreateCImm()
550 Op.Contents.CI = CI; in CreateCImm()
551 return Op; in CreateCImm()
555 MachineOperand Op(MachineOperand::MO_FPImmediate); in CreateFPImm()
556 Op.Contents.CFP = CFP; in CreateFPImm()
557 return Op; in CreateFPImm()
567 MachineOperand Op(MachineOperand::MO_Register);
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| D | MachineRegisterInfo.h | 509 MachineOperand *Op; variable
510 explicit defusechain_iterator(MachineOperand *op) : Op(op) { in defusechain_iterator()
527 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} in defusechain_iterator()
528 defusechain_iterator() : Op(0) {} in defusechain_iterator()
531 return Op == x.Op;
538 bool atEnd() const { return Op == 0; } in atEnd()
542 assert(Op && "Cannot increment end iterator!");
543 Op = getNextOperandForReg(Op);
547 if (Op) {
548 if (Op->isUse())
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 54 SDValue LegalizeOp(SDValue Op);
56 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
58 SDValue UnrollVSETCC(SDValue Op);
63 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
65 SDValue ExpandSEXTINREG(SDValue Op);
68 SDValue ExpandVSELECT(SDValue Op);
69 SDValue ExpandSELECT(SDValue Op);
70 SDValue ExpandLoad(SDValue Op);
71 SDValue ExpandStore(SDValue Op);
72 SDValue ExpandFNEG(SDValue Op);
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| D | TargetLowering.cpp | 263 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, in ShrinkDemandedConstant() argument
265 DebugLoc dl = Op.getDebugLoc(); in ShrinkDemandedConstant()
268 switch (Op.getOpcode()) { in ShrinkDemandedConstant()
273 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); in ShrinkDemandedConstant()
276 if (Op.getOpcode() == ISD::XOR && in ShrinkDemandedConstant()
282 EVT VT = Op.getValueType(); in ShrinkDemandedConstant()
283 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), in ShrinkDemandedConstant()
287 return CombineTo(Op, New); in ShrinkDemandedConstant()
302 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, in ShrinkDemandedOp() argument
306 assert(Op.getNumOperands() == 2 && in ShrinkDemandedOp()
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 62 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op, in printSSECC() argument
64 int64_t Imm = MI->getOperand(Op).getImm() & 0xf; in printSSECC()
86 void X86ATTInstPrinter::printAVXCC(const MCInst *MI, unsigned Op, in printAVXCC() argument
88 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f; in printAVXCC()
132 const MCOperand &Op = MI->getOperand(OpNo); in printPCRelImm() local
133 if (Op.isImm()) in printPCRelImm()
134 O << formatImm(Op.getImm()); in printPCRelImm()
136 assert(Op.isExpr() && "unknown pcrel immediate operand"); in printPCRelImm()
139 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); in printPCRelImm()
147 O << *Op.getExpr(); in printPCRelImm()
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| D | X86IntelInstPrinter.cpp | 52 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op, in printSSECC() argument
54 int64_t Imm = MI->getOperand(Op).getImm() & 0xf; in printSSECC()
76 void X86IntelInstPrinter::printAVXCC(const MCInst *MI, unsigned Op, in printAVXCC() argument
78 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f; in printAVXCC()
120 const MCOperand &Op = MI->getOperand(OpNo); in printPCRelImm() local
121 if (Op.isImm()) in printPCRelImm()
122 O << Op.getImm(); in printPCRelImm()
124 assert(Op.isExpr() && "unknown pcrel immediate operand"); in printPCRelImm()
127 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); in printPCRelImm()
135 O << *Op.getExpr(); in printPCRelImm()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 92 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) in LowerOperation() argument
94 switch (Op.getOpcode()) { in LowerOperation()
96 Op.getNode()->dump(); in LowerOperation()
101 case ISD::SDIV: return LowerSDIV(Op, DAG); in LowerOperation()
102 case ISD::SREM: return LowerSREM(Op, DAG); in LowerOperation()
103 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
104 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
106 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); in LowerOperation()
107 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
109 return Op; in LowerOperation()
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| D | AMDGPUISelLowering.h | 27 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
28 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
39 bool isHWTrueValue(SDValue Op) const;
40 bool isHWFalseValue(SDValue Op) const;
59 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
60 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
61 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
62 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
75 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
92 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
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| D | AMDILISelLowering.cpp | 258 const SDValue Op, in computeMaskedBitsForTargetNode() argument
266 switch (Op.getOpcode()) { in computeMaskedBitsForTargetNode()
270 Op.getOperand(1), in computeMaskedBitsForTargetNode()
276 Op.getOperand(0), in computeMaskedBitsForTargetNode()
296 AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const { in LowerSDIV() argument
297 EVT OVT = Op.getValueType(); in LowerSDIV()
300 DST = LowerSDIV64(Op, DAG); in LowerSDIV()
302 DST = LowerSDIV32(Op, DAG); in LowerSDIV()
305 DST = LowerSDIV24(Op, DAG); in LowerSDIV()
307 DST = SDValue(Op.getNode(), 0); in LowerSDIV()
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| D | SIInsertWaits.cpp | 78 bool isOpRelevant(MachineOperand &Op);
81 RegInterval getRegInterval(MachineOperand &Op);
136 MachineOperand &Op = MI.getOperand(0); in getHwCounts() local
137 assert(Op.isReg() && "First LGKM operand must be a register!"); in getHwCounts()
139 unsigned Reg = Op.getReg(); in getHwCounts()
150 bool SIInsertWaits::isOpRelevant(MachineOperand &Op) { in isOpRelevant() argument
153 if (!Op.isReg()) in isOpRelevant()
157 if (Op.isDef()) in isOpRelevant()
161 MachineInstr &MI = *Op.getParent(); in isOpRelevant()
173 return Op.isIdenticalTo(*I); in isOpRelevant()
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| /external/llvm/include/llvm/MC/ |
| D | MCInst.h | 112 MCOperand Op; in CreateReg() local
113 Op.Kind = kRegister; in CreateReg()
114 Op.RegVal = Reg; in CreateReg()
115 return Op; in CreateReg()
118 MCOperand Op; in CreateImm() local
119 Op.Kind = kImmediate; in CreateImm()
120 Op.ImmVal = Val; in CreateImm()
121 return Op; in CreateImm()
124 MCOperand Op; in CreateFPImm() local
125 Op.Kind = kFPImmediate; in CreateFPImm()
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| D | MCWin64EH.h | 36 MCWin64EHInstruction(OpType Op, MCSymbol *L, unsigned Reg) in MCWin64EHInstruction() argument
37 : Operation(Op), Label(L), Offset(0), Register(Reg) { in MCWin64EHInstruction()
38 assert(Op == Win64EH::UOP_PushNonVol); in MCWin64EHInstruction()
43 MCWin64EHInstruction(OpType Op, MCSymbol *L, unsigned Reg, unsigned Off) in MCWin64EHInstruction() argument
44 : Operation(Op), Label(L), Offset(Off), Register(Reg) { in MCWin64EHInstruction()
45 assert(Op == Win64EH::UOP_SetFPReg || in MCWin64EHInstruction()
46 Op == Win64EH::UOP_SaveNonVol || in MCWin64EHInstruction()
47 Op == Win64EH::UOP_SaveNonVolBig || in MCWin64EHInstruction()
48 Op == Win64EH::UOP_SaveXMM128 || in MCWin64EHInstruction()
49 Op == Win64EH::UOP_SaveXMM128Big); in MCWin64EHInstruction()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 526 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
547 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
564 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
572 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
595 virtual void LowerAsmOperandForConstraint(SDValue Op,
716 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
785 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
791 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
792 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
793 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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| /external/llvm/lib/Target/MBlaze/AsmParser/ |
| D | MBlazeAsmParser.cpp | 228 MBlazeOperand *Op = new MBlazeOperand(Token); in CreateToken() local
229 Op->Tok.Data = Str.data(); in CreateToken()
230 Op->Tok.Length = Str.size(); in CreateToken()
231 Op->StartLoc = S; in CreateToken()
232 Op->EndLoc = S; in CreateToken()
233 return Op; in CreateToken()
237 MBlazeOperand *Op = new MBlazeOperand(Register); in CreateReg() local
238 Op->Reg.RegNum = RegNum; in CreateReg()
239 Op->StartLoc = S; in CreateReg()
240 Op->EndLoc = E; in CreateReg()
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| /external/llvm/lib/Bitcode/Reader/ |
| D | BitstreamReader.cpp | 85 void BitstreamCursor::readAbbreviatedLiteral(const BitCodeAbbrevOp &Op, in readAbbreviatedLiteral() argument
87 assert(Op.isLiteral() && "Not a literal"); in readAbbreviatedLiteral()
89 Vals.push_back(Op.getLiteralValue()); in readAbbreviatedLiteral()
92 void BitstreamCursor::readAbbreviatedField(const BitCodeAbbrevOp &Op, in readAbbreviatedField() argument
94 assert(!Op.isLiteral() && "Use ReadAbbreviatedLiteral for literals!"); in readAbbreviatedField()
97 switch (Op.getEncoding()) { in readAbbreviatedField()
102 Vals.push_back(Read((unsigned)Op.getEncodingData())); in readAbbreviatedField()
105 Vals.push_back(ReadVBR64((unsigned)Op.getEncodingData())); in readAbbreviatedField()
113 void BitstreamCursor::skipAbbreviatedField(const BitCodeAbbrevOp &Op) { in skipAbbreviatedField() argument
114 assert(!Op.isLiteral() && "Use ReadAbbreviatedLiteral for literals!"); in skipAbbreviatedField()
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| /external/llvm/lib/Transforms/Scalar/ |
| D | Reassociate.cpp | 53 Value *Op; member
54 ValueEntry(unsigned R, Value *O) : Rank(R), Op(O) {} in ValueEntry()
67 << *Ops[0].Op->getType() << '\t'; in PrintOps()
70 WriteAsOperand(dbgs(), Ops[i].Op, false, M); in PrintOps()
468 Value *Op = I->getOperand(OpIdx); in LinearizeExprTree() local
470 DEBUG(dbgs() << "OPERAND: " << *Op << " (" << Weight << ")\n"); in LinearizeExprTree()
471 assert(!Op->use_empty() && "No uses, so how did we get to it?!"); in LinearizeExprTree()
475 if (BinaryOperator *BO = isReassociableOp(Op, Opcode)) { in LinearizeExprTree()
476 assert(Visited.insert(Op) && "Not first visit!"); in LinearizeExprTree()
477 DEBUG(dbgs() << "DIRECT ADD: " << *Op << " (" << Weight << ")\n"); in LinearizeExprTree()
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| /external/clang/lib/CodeGen/ |
| D | CGExprComplex.cpp | 140 ComplexPairTy EmitCast(CastExpr::CastKind CK, Expr *Op, QualType DestTy);
219 ComplexPairTy EmitBinAdd(const BinOpInfo &Op);
220 ComplexPairTy EmitBinSub(const BinOpInfo &Op);
221 ComplexPairTy EmitBinMul(const BinOpInfo &Op);
222 ComplexPairTy EmitBinDiv(const BinOpInfo &Op);
376 ComplexPairTy ComplexExprEmitter::EmitCast(CastExpr::CastKind CK, Expr *Op, in EmitCast() argument
388 return Visit(Op); in EmitCast()
391 LValue origLV = CGF.EmitLValue(Op); in EmitCast()
444 llvm::Value *Elt = CGF.EmitScalarExpr(Op); in EmitCast()
448 Elt = CGF.EmitScalarConversion(Elt, Op->getType(), DestTy); in EmitCast()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.h | 90 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
142 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
143 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
144 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
145 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
146 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
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| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| D | MSP430InstPrinter.cpp | 36 const MCOperand &Op = MI->getOperand(OpNo); in printPCRelImmOperand() local
37 if (Op.isImm()) in printPCRelImmOperand()
38 O << Op.getImm(); in printPCRelImmOperand()
40 assert(Op.isExpr() && "unknown pcrel immediate operand"); in printPCRelImmOperand()
41 O << *Op.getExpr(); in printPCRelImmOperand()
48 const MCOperand &Op = MI->getOperand(OpNo); in printOperand() local
49 if (Op.isReg()) { in printOperand()
50 O << getRegisterName(Op.getReg()); in printOperand()
51 } else if (Op.isImm()) { in printOperand()
52 O << '#' << Op.getImm(); in printOperand()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 175 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
199 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
200 SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
201 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
202 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
203 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
204 SDValue LowerF128ToCall(SDValue Op, SelectionDAG &DAG,
206 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
207 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
208 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, bool IsSigned) const;
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| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 15 class Op;
17 def OP_NONE : Op;
18 def OP_UNAVAILABLE : Op;
19 def OP_ADD : Op;
20 def OP_ADDL : Op;
21 def OP_ADDW : Op;
22 def OP_SUB : Op;
23 def OP_SUBL : Op;
24 def OP_SUBW : Op;
25 def OP_MUL : Op;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 164 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
193 SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
195 SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
197 SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
313 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
314 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
315 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
316 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
317 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
318 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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| /external/llvm/lib/Target/R600/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 28 const MCOperand &Op = MI->getOperand(OpNo); in printOperand() local
29 if (Op.isReg()) { in printOperand()
30 switch (Op.getReg()) { in printOperand()
33 default: O << getRegisterName(Op.getReg()); break; in printOperand()
35 } else if (Op.isImm()) { in printOperand()
36 O << Op.getImm(); in printOperand()
37 } else if (Op.isFPImm()) { in printOperand()
38 O << Op.getFPImm(); in printOperand()
39 } else if (Op.isExpr()) { in printOperand()
40 const MCExpr *Exp = Op.getExpr(); in printOperand()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 97 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
100 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
103 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 372 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
382 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
416 virtual void LowerAsmOperandForConstraint(SDValue Op,
481 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
483 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
484 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
485 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
486 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
487 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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