| /external/llvm/lib/Target/X86/ |
| D | X86InstrCMovSetCC.td | 81 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
94 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
95 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
96 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
97 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
98 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
99 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
100 defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal
101 defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than
102 defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set
[all …]
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| D | X86TargetTransformInfo.cpp | 287 { ISD::SETCC, MVT::v2f64, 1 }, in getCmpSelInstrCost()
288 { ISD::SETCC, MVT::v4f32, 1 }, in getCmpSelInstrCost()
289 { ISD::SETCC, MVT::v2i64, 1 }, in getCmpSelInstrCost()
290 { ISD::SETCC, MVT::v4i32, 1 }, in getCmpSelInstrCost()
291 { ISD::SETCC, MVT::v8i16, 1 }, in getCmpSelInstrCost()
292 { ISD::SETCC, MVT::v16i8, 1 }, in getCmpSelInstrCost()
296 { ISD::SETCC, MVT::v4f64, 1 }, in getCmpSelInstrCost()
297 { ISD::SETCC, MVT::v8f32, 1 }, in getCmpSelInstrCost()
299 { ISD::SETCC, MVT::v4i64, 4 }, in getCmpSelInstrCost()
300 { ISD::SETCC, MVT::v8i32, 4 }, in getCmpSelInstrCost()
[all …]
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| D | X86ISelLowering.cpp | 462 setOperationAction(ISD::SETCC , MVT::i8 , Custom); in X86TargetLowering()
463 setOperationAction(ISD::SETCC , MVT::i16 , Custom); in X86TargetLowering()
464 setOperationAction(ISD::SETCC , MVT::i32 , Custom); in X86TargetLowering()
465 setOperationAction(ISD::SETCC , MVT::f32 , Custom); in X86TargetLowering()
466 setOperationAction(ISD::SETCC , MVT::f64 , Custom); in X86TargetLowering()
467 setOperationAction(ISD::SETCC , MVT::f80 , Custom); in X86TargetLowering()
470 setOperationAction(ISD::SETCC , MVT::i64 , Custom); in X86TargetLowering()
801 setOperationAction(ISD::SETCC, VT, Expand); in X86TargetLowering()
911 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); in X86TargetLowering()
912 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); in X86TargetLowering()
[all …]
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| D | X86ISelLowering.h | 91 SETCC, enumerator
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 75 setTargetDAGCombine(ISD::SETCC); in SITargetLowering()
281 if (Intr->getOpcode() == ISD::SETCC) { in LowerBRCOND()
363 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC); in LowerSELECT_CC()
388 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0), in PerformDAGCombine()
394 case ISD::SETCC: { in PerformDAGCombine()
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| D | R600ISelLowering.cpp | 51 setOperationAction(ISD::SETCC, MVT::v4i32, Expand); in R600TargetLowering()
68 setOperationAction(ISD::SETCC, MVT::i32, Expand); in R600TargetLowering()
69 setOperationAction(ISD::SETCC, MVT::f32, Expand); in R600TargetLowering()
468 ISD::SETCC, in LowerFPTOUINT()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 351 SETCC, enumerator
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| D | SelectionDAG.h | 617 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 52 SETCC, enumerator
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| D | MSP430ISelLowering.cpp | 112 setOperationAction(ISD::SETCC, MVT::i8, Custom); in MSP430TargetLowering()
113 setOperationAction(ISD::SETCC, MVT::i16, Custom); in MSP430TargetLowering()
195 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 32 SETCC, enumerator
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 108 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AArch64TargetLowering()
109 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AArch64TargetLowering()
110 setOperationAction(ISD::SETCC, MVT::f32, Custom); in AArch64TargetLowering()
111 setOperationAction(ISD::SETCC, MVT::f64, Custom); in AArch64TargetLowering()
226 setOperationAction(ISD::SETCC, MVT::f128, Custom); in AArch64TargetLowering()
776 case AArch64ISD::SETCC: return "AArch64ISD::SETCC"; in getTargetNodeName()
1624 return DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS, in getSelectableIntSetCC()
1693 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit, in LowerBRCOND()
1742 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS, in LowerBR_CC()
2135 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS, in LowerSELECT_CC()
[all …]
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| D | AArch64ISelLowering.h | 81 SETCC, enumerator
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; in ScalarizeVectorResult()
309 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); in ScalarizeVecRes_SETCC()
336 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, in ScalarizeVecRes_VSETCC()
512 case ISD::SETCC: in SplitVectorResult()
1044 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; in SplitVectorOperand()
1309 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); in SplitVecOp_VSETCC()
1310 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); in SplitVecOp_VSETCC()
1372 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; in WidenVectorResult()
2096 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT, in WidenVecRes_SETCC()
2151 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), in WidenVecRes_VSETCC()
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| D | LegalizeVectorOps.cpp | 221 case ISD::SETCC: in LegalizeOp()
296 else if (Node->getOpcode() == ISD::SETCC) in LegalizeOp()
756 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT), in UnrollVSETCC()
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| D | DAGCombiner.cpp | 547 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
1131 case ISD::SETCC: return visitSETCC(N); in visit()
2638 TLI.isOperationLegal(ISD::SETCC, in visitAND()
3150 TLI.isOperationLegal(ISD::SETCC, in visitOR()
3419 case ISD::SETCC: in visitXOR()
4151 if (N0.getOpcode() == ISD::SETCC) { in visitSELECT()
4192 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) in visitSELECT_CC()
4230 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
4292 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), in ExtendSetCCUses()
4453 if (N0.getOpcode() == ISD::SETCC) { in visitSIGN_EXTEND()
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| D | TargetLowering.cpp | 190 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, getSetCCResultType(RetVT), in softenSetCCOperands()
193 NewLHS = DAG.getNode(ISD::SETCC, dl, getSetCCResultType(RetVT), NewLHS, in softenSetCCOperands()
1165 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { in SimplifySetCC()
1270 (isOperationLegal(ISD::SETCC, newVT) && in SimplifySetCC()
1313 if (N0.getOpcode() == ISD::SETCC && in SimplifySetCC()
1361 Op0.getOperand(0).getOpcode() == ISD::SETCC && in SimplifySetCC()
1362 Op0.getOperand(1).getOpcode() == ISD::SETCC) { in SimplifySetCC()
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| D | LegalizeDAG.cpp | 1186 case ISD::SETCC: in LegalizeOp()
1189 Node->getOpcode() == ISD::SETCC ? 2 : 1; in LegalizeOp()
3556 if (Tmp1.getOpcode() == ISD::SETCC) { in ExpandNode()
3603 if (Tmp2.getOpcode() == ISD::SETCC) { in ExpandNode()
3620 case ISD::SETCC: { in ExpandNode()
3738 Node->getOpcode() == ISD::SETCC) { in PromoteNode()
3878 case ISD::SETCC: { in PromoteNode()
3887 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), in PromoteNode()
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| D | SelectionDAGDumper.cpp | 188 case ISD::SETCC: return "setcc"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 70 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; in PromoteIntegerResult()
786 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; in PromoteIntegerOperand()
2476 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; in ExpandIntegerOperand()
2578 Tmp2 = DAG.getNode(ISD::SETCC, dl, in IntegerExpandSetCCOperands()
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| D | LegalizeFloatTypes.cpp | 616 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break; in SoftenFloatOperand()
1247 case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break; in ExpandFloatOperand()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 736 setOperationAction(ISD::SETCC, MVT::i32, Expand); in SparcTargetLowering()
737 setOperationAction(ISD::SETCC, MVT::f32, Expand); in SparcTargetLowering()
738 setOperationAction(ISD::SETCC, MVT::f64, Expand); in SparcTargetLowering()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 223 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); in MipsTargetLowering()
237 setOperationAction(ISD::SETCC, MVT::f32, Custom); in MipsTargetLowering()
238 setOperationAction(ISD::SETCC, MVT::f64, Custom); in MipsTargetLowering()
662 if (Op.getOpcode() != ISD::SETCC) in createFPCmp()
700 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
907 case ISD::SETCC: return lowerSETCC(Op, DAG); in LowerOperation()
1608 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty), in lowerSELECT_CC()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1228 case ICmp: return ISD::SETCC; in InstructionOpcodeToISD()
1229 case FCmp: return ISD::SETCC; in InstructionOpcodeToISD()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 143 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); in MBlazeTargetLowering()
|