Searched refs:SETOEQ (Results 1 – 19 of 19) sorted by relevance
| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 153 case FCmpInst::FCMP_OEQ: return ISD::SETOEQ; in getFCmpCondCode()
174 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 732 SETOEQ, // 0 0 0 1 True if ordered and equal enumerator
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 580 case ISD::SETOEQ: in getPredicateForSetCC()
615 case ISD::SETOEQ: in getCRIdxForSetCC()
679 case ISD::SETOEQ: in getVCmpInst()
810 case ISD::SETOEQ: in SelectSETCC()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUInstructions.td | 42 case ISD::SETOEQ: case ISD::SETUEQ:
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| D | AMDGPUISelLowering.cpp | 198 case ISD::SETOEQ: in LowerMinMax()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1127 setCondCodeAction(ISD::SETOEQ, MVT::f32, Legal); in HexagonTargetLowering()
1128 setCondCodeAction(ISD::SETOEQ, MVT::f64, Legal); in HexagonTargetLowering()
1220 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); in HexagonTargetLowering()
1223 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeInstrFPU.td | 146 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOEQ),
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 289 case ISD::SETOEQ: return "setoeq"; in getOperationName()
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| D | TargetLowering.cpp | 113 case ISD::SETOEQ: in softenSetCCOperands()
1578 if (Cond == ISD::SETOEQ && in SimplifySetCC()
1591 if (Cond == ISD::SETOEQ && in SimplifySetCC()
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| D | LegalizeDAG.cpp | 1612 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT) in LegalizeSetCCCondCode()
1615 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break; in LegalizeSetCCCondCode()
1621 case ISD::SETOEQ: in LegalizeSetCCCondCode()
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| D | LegalizeFloatTypes.cpp | 1286 LHSHi, RHSHi, ISD::SETOEQ); in FloatExpandSetCCOperands()
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| D | SelectionDAG.cpp | 310 case ISD::SETOEQ: // SETEQ & SETU[LG]E in getSetCCAndOperation()
1567 case ISD::SETOEQ: in FoldSetCC()
1609 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); in FoldSetCC()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 498 def SETOEQ : CondCode; def SETOGT : CondCode;
829 (setcc node:$lhs, node:$rhs, SETOEQ)>;
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 668 case ISD::SETOEQ: return SPCC::FCC_E; in FPCondCCodeToFCC()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1159 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; in FPCCToARMCC()
3106 if (CC == ISD::SETOEQ) in OptimizeVFPBrcond()
3159 (CC == ISD::SETEQ || CC == ISD::SETOEQ || in LowerBR_CC()
3788 case ISD::SETOEQ: in LowerVSETCC()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 952 (setcc node:$lhs, node:$rhs, SETOEQ)>;
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 248 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); in X86TargetLowering()
249 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); in X86TargetLowering()
250 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); in X86TargetLowering()
3272 case ISD::SETOEQ: in TranslateX86CC()
9271 case ISD::SETOEQ: in LowerVSETCC()
9927 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { in LowerBRCOND()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1636 case ISD::SETOEQ: CondCode = A64CC::EQ; break; in FPCCToA64CC()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 624 case ISD::SETOEQ: return Mips::FCOND_OEQ; in FPCondCCodeToFCC()
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