| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 710 SEXTLOAD, enumerator
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| D | SelectionDAGNodes.h | 1824 cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 567 LD->getExtensionType() == ISD::SEXTLOAD) { in SelectIndexedLoad()
802 LD->getExtensionType() != ISD::SEXTLOAD || in SelectMul()
828 LD->getExtensionType() != ISD::SEXTLOAD || in SelectMul()
982 LD->getExtensionType() != ISD::SEXTLOAD || in SelectTruncate()
1007 LD->getExtensionType() != ISD::SEXTLOAD || in SelectTruncate()
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| D | HexagonISelLowering.cpp | 650 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPostIndexedAddressParts()
1311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 95 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in MBlazeTargetLowering()
98 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); in MBlazeTargetLowering()
99 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); in MBlazeTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 249 Extension = ISD::SEXTLOAD; in SelectToLitPool()
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| D | AArch64ISelLowering.cpp | 76 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in AArch64TargetLowering()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); in MSP430TargetLowering()
90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 453 case ISD::SEXTLOAD: OS << ", sext"; break; in print_details()
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| D | DAGCombiner.cpp | 2712 if (LN0->getExtensionType() != ISD::SEXTLOAD && in visitAND()
4368 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { in visitSIGN_EXTEND()
4375 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, in visitSIGN_EXTEND()
4398 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { in visitSIGN_EXTEND()
4399 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, in visitSIGN_EXTEND()
4420 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && in visitSIGN_EXTEND()
4430 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, in visitSIGN_EXTEND()
4695 if (LN0->getExtensionType() != ISD::SEXTLOAD) { in visitZERO_EXTEND()
5044 ExtType = ISD::SEXTLOAD; in ReduceLoadWidth()
5083 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD) in ReduceLoadWidth()
[all …]
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| D | LegalizeVectorOps.cpp | 481 case ISD::SEXTLOAD: in ExpandLoad()
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| D | LegalizeDAG.cpp | 953 if (ExtType == ISD::SEXTLOAD) in LegalizeLoadOps()
1087 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break; in LegalizeLoadOps()
1112 if (ExtType == ISD::SEXTLOAD) in LegalizeLoadOps()
3583 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, in ExpandNode()
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| D | LegalizeIntegerTypes.cpp | 1818 if (ExtType == ISD::SEXTLOAD) { in ExpandIntRes_LOAD()
1890 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, in ExpandIntRes_LOAD()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelDAGToDAG.cpp | 209 if ((LD->getExtensionType() == ISD::SEXTLOAD)) in SelectLoad()
377 if (ExtensionType == ISD::SEXTLOAD) in SelectLoadVector()
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| D | NVPTXISelLowering.cpp | 163 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in NVPTXTargetLowering()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 1057 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select()
1091 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select()
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| D | PPCISelLowering.cpp | 91 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in PPCTargetLowering()
92 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); in PPCTargetLowering()
392 setLoadExtAction(ISD::SEXTLOAD, VT, Expand); in PPCTargetLowering()
1226 LD->getExtensionType() == ISD::SEXTLOAD && in getPreIndexedAddressParts()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 274 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; in LowerFormalArguments()
701 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in SparcTargetLowering()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 132 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in XCoreTargetLowering()
134 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); in XCoreTargetLowering()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 213 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in MipsTargetLowering()
373 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); in MipsTargetLowering()
1550 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, in lowerBR_JT()
2162 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || in lowerLOAD()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1440 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD) in SelectARMIndexedLoad()
1444 if (LD->getExtensionType() == ISD::SEXTLOAD) { in SelectARMIndexedLoad()
1493 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD; in SelectT2IndexedLoad()
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| D | ARMISelLowering.cpp | 449 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); in ARMTargetLowering()
606 setLoadExtAction(ISD::SEXTLOAD, Tys[i], Legal); in ARMTargetLowering()
621 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in ARMTargetLowering()
5164 case ISD::SEXTLOAD: ExtOp = ISD::SIGN_EXTEND; break; in SkipLoadExtensionForVMULL()
9875 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPreIndexedAddressParts()
9914 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPostIndexedAddressParts()
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| /external/llvm/lib/Transforms/Scalar/ |
| D | CodeGenPrepare.cpp | 1719 LType = ISD::SEXTLOAD; in MoveExtToFormExtLoad()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 621 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 237 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in X86TargetLowering()
821 setLoadExtAction(ISD::SEXTLOAD, VT, Expand); in X86TargetLowering()
16574 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) { in PerformLOADCombine()
16582 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) in PerformLOADCombine()
16608 if (Ext == ISD::SEXTLOAD && NumLoads > 1) in PerformLOADCombine()
16612 if (Ext == ISD::SEXTLOAD && RegSz == 256) in PerformLOADCombine()
16665 if (Ext == ISD::SEXTLOAD) { in PerformLOADCombine()
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