| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 223 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
226 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
228 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
230 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
232 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
234 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
236 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
238 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
240 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
242 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
[all …]
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| D | ARMISelLowering.cpp | 109 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForNEON()
114 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addTypeForNEON()
559 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); in ARMTargetLowering()
829 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
3280 case ISD::SINT_TO_FP: in LowerVectorINT_TO_FP()
3282 Opc = ISD::SINT_TO_FP; in LowerVectorINT_TO_FP()
3304 case ISD::SINT_TO_FP: in LowerINT_TO_FP()
5321 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
5322 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); in LowerSDIV_v4i8()
5351 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
[all …]
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| /external/llvm/test/CodeGen/R600/ |
| D | dagcombiner-bug-illegal-vec4-int-to-fp.ll | 7 ; ISD::UINT_TO_FP and ISD::SINT_TO_FP opcodes.
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 254 case ISD::SINT_TO_FP: in LegalizeOp()
268 case ISD::SINT_TO_FP: in LegalizeOp()
699 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand || in ExpandUINT_TO_FLOAT()
725 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI); in ExpandUINT_TO_FLOAT()
727 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO); in ExpandUINT_TO_FLOAT()
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| D | LegalizeFloatTypes.cpp | 98 case ISD::SINT_TO_FP: in SoftenFloatResult()
564 bool Signed = N->getOpcode() == ISD::SINT_TO_FP; in SoftenFloatRes_XINT_TO_FP()
825 case ISD::SINT_TO_FP: in ExpandFloatResult()
1148 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP; in ExpandFloatRes_XINT_TO_FP()
1160 Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src); in ExpandFloatRes_XINT_TO_FP()
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| D | LegalizeDAG.cpp | 1168 case ISD::SINT_TO_FP: in LegalizeOp()
2314 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0); in ExpandLegalINT_TO_FP()
2323 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or); in ExpandLegalINT_TO_FP()
2366 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2432 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { in PromoteLegalINT_TO_FP()
2433 OpToUse = ISD::SINT_TO_FP; in PromoteLegalINT_TO_FP()
2902 case ISD::SINT_TO_FP: in ExpandNode()
2904 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, in ExpandNode()
3737 Node->getOpcode() == ISD::SINT_TO_FP || in PromoteNode()
3787 case ISD::SINT_TO_FP: in PromoteNode()
[all …]
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| D | SelectionDAGDumper.cpp | 225 case ISD::SINT_TO_FP: return "sint_to_fp"; in getOperationName()
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| D | LegalizeVectorTypes.cpp | 90 case ISD::SINT_TO_FP: in ScalarizeVectorResult()
546 case ISD::SINT_TO_FP: in SplitVectorResult()
1062 case ISD::SINT_TO_FP: in SplitVectorOperand()
1416 case ISD::SINT_TO_FP: in WidenVectorResult()
2188 case ISD::SINT_TO_FP: in WidenVectorOperand()
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| D | FastISel.cpp | 224 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeRegForValue()
1055 return SelectCast(I, ISD::SINT_TO_FP); in SelectOperator()
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| D | LegalizeIntegerTypes.cpp | 788 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; in PromoteIntegerOperand()
2477 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; in ExpandIntegerOperand()
2794 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ in ExpandIntOp_UINT_TO_FP()
2796 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); in ExpandIntOp_UINT_TO_FP()
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| D | DAGCombiner.cpp | 1146 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); in visit()
6365 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); in visitSINT_TO_FP()
6369 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && in visitSINT_TO_FP()
6427 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { in visitUINT_TO_FP()
6430 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); in visitUINT_TO_FP()
8785 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) { in reduceBuildVecConvertToConvertBuildVec()
8808 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP) in reduceBuildVecConvertToConvertBuildVec()
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| D | SelectionDAGBuilder.cpp | 2821 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); in visitSIToFP()
3690 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); in GetExponent()
3717 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); in expandExp()
4091 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); in expandExp2()
4201 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); in expandPow()
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| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 251 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 }, in getCastInstrCost()
252 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 }, in getCastInstrCost()
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| D | README-FPStack.txt | 49 Add a target specific hook to DAG combiner to handle SINT_TO_FP and
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| D | X86ISelLowering.cpp | 275 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); in X86TargetLowering()
276 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); in X86TargetLowering()
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); in X86TargetLowering()
283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); in X86TargetLowering()
285 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); in X86TargetLowering()
286 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); in X86TargetLowering()
289 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); in X86TargetLowering()
290 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); in X86TargetLowering()
296 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); in X86TargetLowering()
810 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in X86TargetLowering()
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 379 SINT_TO_FP, enumerator
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1153 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1158 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1163 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
1168 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); in HexagonTargetLowering()
1173 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal); in HexagonTargetLowering()
1186 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/R600/ |
| D | AMDILISelLowering.cpp | 434 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia); in LowerSDIV24()
437 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib); in LowerSDIV24()
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| D | R600ISelLowering.cpp | 47 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand); in R600TargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 240 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
241 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
242 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
2322 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG, true); in LowerOperation()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 723 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1154 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 198 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
287 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
409 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
468 setTargetDAGCombine(ISD::SINT_TO_FP); in PPCTargetLowering()
5567 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
6287 case ISD::SINT_TO_FP: in PerformDAGCombine()
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| D | README.txt | 545 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1222 case SIToFP: return ISD::SINT_TO_FP; in InstructionOpcodeToISD()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 390 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
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