| /external/webkit/Source/WebKit/android/content/ |
| D | address_detector.cpp | 722 VA = 52, // VA Virginia in IsZipValidForState() enumerator
753 DC, VA, DC, DC, DC, DC, MD, MD, MD, MD, // 200-209 in IsZipValidForState()
755 VA, VA, VA, VA, VA, VA, VA, VA, VA, VA, // 220-229 in IsZipValidForState()
756 VA, VA, VA, VA, VA, VA, VA, VA, VA, VA, // 230-239 in IsZipValidForState()
757 VA, VA, VA, VA, VA, VA, VA, WV, WV, WV, // 240-249 in IsZipValidForState()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 105 CCValAssign &VA = RVLocs[i]; in LowerReturn() local
106 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
108 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
113 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
166 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments() local
179 if (VA.isRegLoc()) { in LowerFormalArguments()
180 if (VA.needsCustom()) { in LowerFormalArguments()
181 assert(VA.getLocVT() == MVT::f64); in LowerFormalArguments()
183 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments()
209 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
[all …]
|
| /external/clang/test/Parser/ |
| D | cxx-using-declaration.cpp | 4 int VA; variable
9 using A::VA;
15 VA = 1; in main()
|
| /external/clang/test/CXX/special/class.dtor/ |
| D | p3-0x.cpp | 140 struct VA { struct
142 virtual ~VA() {} in ~VA() argument
145 struct VB : VA
149 struct TVB : VA
|
| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 729 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
730 MVT RegVT = VA.getLocVT(); in LowerCall()
734 switch (VA.getLocInfo()) { in LowerCall()
750 if (VA.isRegLoc()) { in LowerCall()
751 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
754 assert(VA.isMemLoc()); in LowerCall()
762 unsigned ArgSize = VA.getValVT().getSizeInBits()/8; in LowerCall()
763 unsigned StackLoc = VA.getLocMemOffset() + 4; in LowerCall()
901 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments() local
904 if (VA.isRegLoc()) { in LowerFormalArguments()
[all …]
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 335 CCValAssign &VA = ArgLocs[i]; in LowerCCCArguments() local
336 if (VA.isRegLoc()) { in LowerCCCArguments()
338 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
350 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
356 if (VA.getLocInfo() == CCValAssign::SExt) in LowerCCCArguments()
358 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
359 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerCCCArguments()
361 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
363 if (VA.getLocInfo() != CCValAssign::Full) in LowerCCCArguments()
364 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerCCCArguments()
[all …]
|
| /external/qemu/ |
| D | ppc-dis.c | 817 #define VA UI + 1 macro
821 #define VB VA + 1
2177 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
2178 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
2179 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
2180 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
2181 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
2182 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
2183 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
2184 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
[all …]
|
| /external/clang/test/Preprocessor/ |
| D | macro_paste_bad.c | 32 #define VA __VA_ ## ARGS__ macro
33 int VA; // expected-warning {{__VA_ARGS__ can only appear in the expansion of a C99 variadic macr… variable
|
| /external/mksh/src/ |
| D | shf.c | 776 #define VA(type) va_arg(args, type) in shf_vfprintf() macro
825 tmp = VA(int); in shf_vfprintf()
886 lnum = (long)VA(ssize_t); in shf_vfprintf()
888 lnum = VA(long); in shf_vfprintf()
890 lnum = (long)(short)VA(int); in shf_vfprintf()
892 lnum = (long)VA(int); in shf_vfprintf()
899 lnum = VA(size_t); in shf_vfprintf()
901 lnum = VA(unsigned long); in shf_vfprintf()
903 lnum = (unsigned long)(unsigned short)VA(int); in shf_vfprintf()
905 lnum = (unsigned long)VA(unsigned int); in shf_vfprintf()
[all …]
|
| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 764 CCValAssign &VA = ValLocs[0]; in X86SelectRet() local
767 if (VA.getLocInfo() != CCValAssign::Full) in X86SelectRet()
770 if (!VA.isRegLoc()) in X86SelectRet()
775 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) in X86SelectRet()
778 unsigned SrcReg = Reg + VA.getValNo(); in X86SelectRet()
780 EVT DstVT = VA.getValVT(); in X86SelectRet()
804 unsigned DstReg = VA.getLocReg(); in X86SelectRet()
813 RetRegs.push_back(VA.getLocReg()); in X86SelectRet()
1805 CCValAssign &VA = ArgLocs[i]; in DoSelectCall() local
1806 unsigned Arg = Args[VA.getValNo()]; in DoSelectCall()
[all …]
|
| /external/skia/src/sfnt/ |
| D | SkOTTable_OS_2.h | 31 struct VA : SkOTTableOS2_VA { } vA; struct
45 SK_COMPILE_ASSERT(sizeof(SkOTTableOS2::Version::VA) == 68, sizeof_SkOTTableOS2__VA_not_68);
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 322 CCValAssign &VA = RVLocs[i]; in LowerReturn() local
324 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
328 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
434 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
435 if (VA.isMemLoc()) { in LowerCall()
458 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
463 switch (VA.getLocInfo()) { in LowerCall()
470 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
473 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
476 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 912 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments() local
923 VA.getLocMemOffset(), in LowerFormalArguments()
929 } else if (VA.isRegLoc()) { in LowerFormalArguments()
930 MVT RegVT = VA.getLocVT(); in LowerFormalArguments()
932 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
936 assert(VA.isMemLoc()); in LowerFormalArguments()
938 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8, in LowerFormalArguments()
939 VA.getLocMemOffset(), true); in LowerFormalArguments()
942 ArgValue = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerFormalArguments()
949 switch (VA.getLocInfo()) { in LowerFormalArguments()
[all …]
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 959 CCValAssign &VA = ArgLocs[i]; in LowerCCCCallTo() local
963 switch (VA.getLocInfo()) { in LowerCCCCallTo()
967 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
970 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
973 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
979 if (VA.isRegLoc()) { in LowerCCCCallTo()
980 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
982 assert(VA.isMemLoc()); in LowerCCCCallTo()
984 int Offset = VA.getLocMemOffset(); in LowerCCCCallTo()
1133 CCValAssign &VA = ArgLocs[i]; in LowerCCCArguments() local
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1916 CCValAssign &VA = ArgLocs[i]; in ProcessCallArgs() local
1917 MVT ArgVT = ArgVTs[VA.getValNo()]; in ProcessCallArgs()
1924 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1926 } else if (VA.needsCustom()) { in ProcessCallArgs()
1928 if (VA.getLocVT() != MVT::f64 || in ProcessCallArgs()
1930 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) in ProcessCallArgs()
1966 CCValAssign &VA = ArgLocs[i]; in ProcessCallArgs() local
1967 unsigned Arg = ArgRegs[VA.getValNo()]; in ProcessCallArgs()
1968 MVT ArgVT = ArgVTs[VA.getValNo()]; in ProcessCallArgs()
1974 switch (VA.getLocInfo()) { in ProcessCallArgs()
[all …]
|
| D | ARMISelLowering.cpp | 1245 CCValAssign VA = RVLocs[i]; in LowerCallResult() local
1248 if (VA.needsCustom()) { in LowerCallResult()
1250 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1254 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1255 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1261 if (VA.getLocVT() == MVT::v2f64) { in LowerCallResult()
1266 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1267 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1270 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1271 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
[all …]
|
| D | ARMISelLowering.h | 418 CCValAssign &VA, CCValAssign &NextVA,
422 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
430 const CCValAssign &VA,
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrFormats.td | 833 // E-1 VA-Form
840 bits<5> VA;
847 let Inst{11-15} = VA;
858 bits<5> VA;
865 let Inst{11-15} = VA;
875 bits<5> VA;
882 let Inst{11-15} = VA;
894 bits<5> VA;
900 let Inst{11-15} = VA;
908 let VA = VD;
[all …]
|
| D | PPCISelLowering.cpp | 1925 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments_32SVR4() local
1928 if (VA.isRegLoc()) { in LowerFormalArguments_32SVR4()
1930 EVT ValVT = VA.getValVT(); in LowerFormalArguments_32SVR4()
1953 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
1959 assert(VA.isMemLoc()); in LowerFormalArguments_32SVR4()
1961 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; in LowerFormalArguments_32SVR4()
1962 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), in LowerFormalArguments_32SVR4()
1967 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, in LowerFormalArguments_32SVR4()
3289 CCValAssign &VA = RVLocs[i]; in LowerCallResult() local
3290 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCallResult()
[all …]
|
| /external/clang/lib/Analysis/ |
| D | LiveVariables.cpp | 308 for (const VariableArrayType* VA = FindVA(VD->getType()); in Visit() local
309 VA != 0; VA = FindVA(VA->getElementType())) { in Visit()
310 AddLiveStmt(val.liveStmts, LV.SSetFact, VA->getSizeExpr()); in Visit()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2645 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
2646 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); in LowerCall()
2663 switch (VA.getLocInfo()) { in LowerCall()
2666 if (VA.isRegLoc()) { in LowerCall()
2678 unsigned LocRegLo = VA.getLocReg(); in LowerCall()
2699 if (VA.isRegLoc()) { in LowerCall()
2700 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
2705 assert(VA.isMemLoc()); in LowerCall()
2709 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), in LowerCall()
2852 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments() local
[all …]
|
| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 159 CCValAssign &VA = ArgLocs[ArgIdx++]; in LowerFormalArguments() local
160 assert(VA.isRegLoc() && "Parameter must be in a register!"); in LowerFormalArguments()
162 unsigned Reg = VA.getLocReg(); in LowerFormalArguments()
163 MVT VT = VA.getLocVT(); in LowerFormalArguments()
|
| /external/icu4c/data/region/ |
| D | my.txt | 211 VA{"ဗာတီကန်"}
|
| /external/icu4c/ |
| D | runConfigureICU | 44 Linux/VA Use the IBM Visual Age compiler on Power PC Linux
219 Linux/VA)
|
| /external/icu4c/data/translit/ |
| D | Tamil_InterIndic.txt | 46 வ→\uE035; # LETTER VA
|