| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 134 if (i+II.getNumDefs() < II.getNumOperands()) { in EmitCopyFromReg()
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
214 for (unsigned i = 0; i < II.getNumDefs(); ++i) { in CreateVirtualRegisters()
721 countOperands(Node, II.getNumOperands() - II.getNumDefs(), NumImpUses); in EmitMachineNode()
722 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; in EmitMachineNode()
745 bool HasOptPRefs = II.getNumDefs() > NumResults; in EmitMachineNode()
748 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; in EmitMachineNode()
750 AddOperand(MIB, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, in EmitMachineNode()
781 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { in EmitMachineNode()
782 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; in EmitMachineNode()
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| D | FastISel.cpp | 1211 if (II.getNumDefs() >= 1) in FastEmitInst_r()
1231 if (II.getNumDefs() >= 1) in FastEmitInst_rr()
1253 if (II.getNumDefs() >= 1) in FastEmitInst_rrr()
1276 if (II.getNumDefs() >= 1) in FastEmitInst_ri()
1297 if (II.getNumDefs() >= 1) in FastEmitInst_rii()
1320 if (II.getNumDefs() >= 1) in FastEmitInst_rf()
1342 if (II.getNumDefs() >= 1) in FastEmitInst_rri()
1366 if (II.getNumDefs() >= 1) in FastEmitInst_rrii()
1388 if (II.getNumDefs() >= 1) in FastEmitInst_i()
1404 if (II.getNumDefs() >= 1) in FastEmitInst_ii()
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| D | ScheduleDAGSDNodes.cpp | 124 if (ResNo >= II.getNumDefs() && in CheckForPhysRegDependency()
125 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { in CheckForPhysRegDependency()
453 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs()) in AddSchedEdges()
544 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs(); in InitNodeNumDefs()
631 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); in computeOperandLatency()
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| D | ScheduleDAGRRList.cpp | 1194 unsigned NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
1977 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in MayReduceRegPressure()
2024 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in RegPressureDiff()
2154 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2171 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2691 unsigned NumRes = MCID.getNumDefs(); in canClobber()
2749 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in canClobberPhysRegDefs()
2918 unsigned NumRes = MCID.getNumDefs(); in AddPseudoTwoAddrDeps()
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| D | ResourcePriorityQueue.cpp | 559 NodeNumDefs = std::min(N->getNumValues(), TID.getNumDefs()); in initNumRegDefsLeft()
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| D | ScheduleDAGFast.cpp | 437 unsigned NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 313 unsigned NumDefs = MI->getDesc().getNumDefs(); in optimizeBitcastInstr()
343 NumDefs = DefMI->getDesc().getNumDefs(); in optimizeBitcastInstr()
422 if (MCID.getNumDefs() != 1) in isLoadFoldable()
444 if (MCID.getNumDefs() != 1) in isMoveImmediate()
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| D | ExecutionDepsFix.cpp | 457 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
511 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
521 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
540 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
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| D | TargetInstrInfo.cpp | 121 bool HasDef = MCID.getNumDefs(); in commuteInstruction()
190 SrcOpIdx1 = MCID.getNumDefs(); in findCommutedOpIndices()
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| D | MachineLICM.cpp | 1049 unsigned NumDefs = MI.getDesc().getNumDefs(); in IsCheapInstruction()
1262 if (MID.getNumDefs() != 1) return 0; in ExtractHoistableLoad()
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| D | MachineCSE.cpp | 514 unsigned NumDefs = MI->getDesc().getNumDefs() + in ProcessBlock()
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| D | MachineVerifier.cpp | 807 if (MONum < MCID.getNumDefs()) { in visitMachineOperand()
861 if (MONum < MCID.getNumDefs()) { in visitMachineOperand()
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| D | RegAllocFast.cpp | 954 (hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) { in AllocateBasicBlock()
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| D | TwoAddressInstructionPass.cpp | 1189 if (UnfoldMCID.getNumDefs() == 1) { in tryInstructionTransform()
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| D | RegisterCoalescer.cpp | 759 if (MCID.getNumDefs() != 1) in reMaterializeTrivialDef()
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 179 unsigned getNumDefs() const { in getNumDefs() function
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 556 unsigned NumDefs = Desc->getNumDefs(); in PostISelFolding()
563 assert(!DescE64 || DescE64->getNumDefs() == NumDefs); in PostISelFolding()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 308 if (II.getNumDefs() >= 1) { in FastEmitInst_r()
328 if (II.getNumDefs() >= 1) { in FastEmitInst_rr()
351 if (II.getNumDefs() >= 1) { in FastEmitInst_rrr()
375 if (II.getNumDefs() >= 1) { in FastEmitInst_ri()
397 if (II.getNumDefs() >= 1) { in FastEmitInst_rf()
420 if (II.getNumDefs() >= 1) { in FastEmitInst_rri()
443 if (II.getNumDefs() >= 1) { in FastEmitInst_i()
462 if (II.getNumDefs() >= 1) { in FastEmitInst_ii()
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| D | ARMCodeEmitter.cpp | 1114 unsigned NumDefs = MCID.getNumDefs(); in emitDataProcessingInstruction()
1428 if (MCID.getNumDefs() == 2) in emitMulFrmInstruction()
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| D | ARMBaseInstrInfo.cpp | 2936 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
4094 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def"); in breakPartialRegDependency()
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| D | ARMISelLowering.cpp | 1122 if (MCID.getNumDefs() == 0) in getSchedulingPreference()
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| /external/llvm/lib/MC/MCParser/ |
| D | AsmParser.cpp | 4117 unsigned NumDefs = Desc.getNumDefs(); in parseMSInlineAsm()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 4285 if (MCID.getNumDefs() > 0) { in unfoldMemoryOperand()
4291 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs()) in unfoldMemoryOperand()
|