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Searched refs:vassert (Results 1 – 25 of 35) sorted by relevance

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/external/valgrind/main/VEX/priv/
Dmain_main.c115 vassert(!vex_initdone); in LibVEX_Init()
116 vassert(failure_exit); in LibVEX_Init()
117 vassert(log_bytes); in LibVEX_Init()
118 vassert(debuglevel >= 0); in LibVEX_Init()
120 vassert(vcon->iropt_verbosity >= 0); in LibVEX_Init()
121 vassert(vcon->iropt_level >= 0); in LibVEX_Init()
122 vassert(vcon->iropt_level <= 2); in LibVEX_Init()
123 vassert(vcon->iropt_unroll_thresh >= 0); in LibVEX_Init()
124 vassert(vcon->iropt_unroll_thresh <= 400); in LibVEX_Init()
125 vassert(vcon->guest_max_insns >= 1); in LibVEX_Init()
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Dhost_generic_reg_alloc2.c188 vassert(search_from_instr >= 0); in findMostDistantlyMentionedVReg()
192 vassert(state[k].disp == Bound); in findMostDistantlyMentionedVReg()
212 vassert(0 == ((UShort)vreg->spill_offset % 16)); break; in sanity_check_spill_offset()
214 vassert(0 == ((UShort)vreg->spill_offset % 8)); break; in sanity_check_spill_offset()
227 vassert(used == *size); in ensureRRLRspace()
249 vassert(size >= 0); in sortRRLRarray()
402 vassert(0 == (guest_sizeB % 32)); in doRegisterAllocation()
403 vassert(0 == (LibVEX_N_SPILL_BYTES % 32)); in doRegisterAllocation()
404 vassert(0 == (N_SPILL64S % 4)); in doRegisterAllocation()
409 vassert(instrs_in->arr_used <= 15000); in doRegisterAllocation()
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Dmain_util.c74 vassert(temporary_first == &temporary[0]); in vexAllocSanityCheck()
75 vassert(temporary_last == &temporary[N_TEMPORARY_BYTES-1]); in vexAllocSanityCheck()
76 vassert(permanent_first == &permanent[0]); in vexAllocSanityCheck()
77 vassert(permanent_last == &permanent[N_PERMANENT_BYTES-1]); in vexAllocSanityCheck()
78 vassert(temporary_first <= temporary_curr); in vexAllocSanityCheck()
79 vassert(temporary_curr <= temporary_last); in vexAllocSanityCheck()
80 vassert(permanent_first <= permanent_curr); in vexAllocSanityCheck()
81 vassert(permanent_curr <= permanent_last); in vexAllocSanityCheck()
82 vassert(private_LibVEX_alloc_first <= private_LibVEX_alloc_curr); in vexAllocSanityCheck()
83 vassert(private_LibVEX_alloc_curr <= private_LibVEX_alloc_last); in vexAllocSanityCheck()
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Dhost_ppc_defs.c68 vassert(r >= 0 && r < 32); in ppHRegPPC()
73 vassert(r >= 0 && r < 32); in ppHRegPPC()
78 vassert(r >= 0 && r < 32); in ppHRegPPC()
83 vassert(r >= 0 && r < 32); in ppHRegPPC()
270 vassert(i == *nregs); in getAllocableRegs_PPC()
302 vassert(flag == Pcf_NONE); in mk_PPCCondCode()
304 vassert(flag != Pcf_NONE); in mk_PPCCondCode()
312 vassert(ct != Pct_ALWAYS); in invertCondTest()
321 vassert(idx >= -0x8000 && idx < 0x8000); in PPCAMode_IR()
404 vassert(imm16 != 0x8000); in PPCRH_Imm()
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Dhost_mips_defs.c71 vassert(hregClass(reg) == HRcInt32 || hregClass(reg) == HRcInt64 || in ppHRegMIPS()
79 vassert(r >= 0 && r < 32); in ppHRegMIPS()
84 vassert(r >= 0 && r < 32); in ppHRegMIPS()
89 vassert(r >= 0 && r < 32); in ppHRegMIPS()
622 vassert(i == *nregs); in getAllocableRegs_MIPS()
957 vassert(imm16 != 0x8000); in MIPSRH_Imm()
958 vassert(syned == True || syned == False); in MIPSRH_Imm()
1059 vassert(immR == False); /*there's no nor with an immediate operand!? */ in showMIPSAluOp()
1231 vassert(0 == (argiregs & ~mask)); in MIPSInstr_Call()
1245 vassert(0 == (argiregs & ~mask)); in MIPSInstr_CallAlways()
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Dguest_generic_bb_to_IR.c221 vassert(sizeof(HWord) == sizeof(void*)); in bb_to_IR()
222 vassert(vex_control.guest_max_insns >= 1); in bb_to_IR()
223 vassert(vex_control.guest_max_insns < 100); in bb_to_IR()
224 vassert(vex_control.guest_chase_thresh >= 0); in bb_to_IR()
225 vassert(vex_control.guest_chase_thresh < vex_control.guest_max_insns); in bb_to_IR()
226 vassert(guest_word_type == Ity_I32 || guest_word_type == Ity_I64); in bb_to_IR()
229 vassert(szB_GUEST_IP == 4); in bb_to_IR()
230 vassert((offB_GUEST_IP % 4) == 0); in bb_to_IR()
232 vassert(szB_GUEST_IP == 8); in bb_to_IR()
233 vassert((offB_GUEST_IP % 8) == 0); in bb_to_IR()
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Dhost_mips_isel.c131 vassert(tmp >= 0); in lookupIRTemp()
132 vassert(tmp < env->n_vregmap); in lookupIRTemp()
138 vassert(tmp >= 0); in lookupIRTemp64()
139 vassert(tmp < env->n_vregmap); in lookupIRTemp64()
140 vassert(env->vregmapHI[tmp] != INVALID_HREG); in lookupIRTemp64()
148 vassert(env->mode64); in lookupIRTempPair()
149 vassert(tmp >= 0); in lookupIRTempPair()
150 vassert(tmp < env->n_vregmap); in lookupIRTempPair()
151 vassert(env->vregmapHI[tmp] != INVALID_HREG); in lookupIRTempPair()
191 vassert(n < 256 && (n % 8) == 0); in add_to_sp()
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Dir_opt.c247 vassert(h->used < h->size); in addToHHW()
462 vassert(d2->mAddr == NULL); in flatten_Stmt()
533 vassert((*minoff & ~0xFFFF) == 0); in getArrayBounds()
534 vassert((*maxoff & ~0xFFFF) == 0); in getArrayBounds()
535 vassert(*minoff <= *maxoff); in getArrayBounds()
545 vassert((minoff & ~0xFFFF) == 0); in mk_key_GetPut()
546 vassert((maxoff & ~0xFFFF) == 0); in mk_key_GetPut()
554 vassert((minoff & ~0xFFFF) == 0); in mk_key_GetIPutI()
555 vassert((maxoff & ~0xFFFF) == 0); in mk_key_GetIPutI()
567 vassert(k_lo <= k_hi); in invalidateOverlaps()
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Dhost_amd64_defs.c62 vassert(r >= 0 && r < 16); in ppHRegAMD64()
67 vassert(r >= 0 && r < 6); in ppHRegAMD64()
72 vassert(r >= 0 && r < 16); in ppHRegAMD64()
96 vassert(r >= 0 && r < 16); in ppHRegAMD64_lo32()
219 vassert(shift >= 0 && shift <= 3); in AMD64AMode_IRRS()
629 vassert(op != Aalu_MUL); in AMD64Instr_Alu64M()
670 default: vassert(0); in AMD64Instr_Alu32R()
687 vassert(sz == 4 || sz == 8); in AMD64Instr_Div()
702 vassert(regparms >= 0 && regparms <= 6); in AMD64Instr_Call()
742 vassert(cond != Acc_ALWAYS); in AMD64Instr_CMov64()
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Dhost_s390_defs.c101 vassert(r < 16); in s390_hreg_as_string()
209 vassert(fits_unsigned_12bit(d)); in s390_amode_b12()
226 vassert(fits_signed_20bit(d)); in s390_amode_b20()
243 vassert(fits_unsigned_12bit(d)); in s390_amode_bx12()
244 vassert(b != 0); in s390_amode_bx12()
245 vassert(x != 0); in s390_amode_bx12()
262 vassert(fits_signed_20bit(d)); in s390_amode_bx20()
263 vassert(b != 0); in s390_amode_bx20()
264 vassert(x != 0); in s390_amode_bx20()
459 vassert(offsetB >= 0); in genSpill_S390()
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Dhost_arm_isel.c131 vassert(tmp >= 0); in lookupIRTemp()
132 vassert(tmp < env->n_vregmap); in lookupIRTemp()
138 vassert(tmp >= 0); in lookupIRTemp64()
139 vassert(tmp < env->n_vregmap); in lookupIRTemp64()
140 vassert(env->vregmapHI[tmp] != INVALID_HREG); in lookupIRTemp64()
265 vassert(sh >= 0 && sh < 32); in ROR32()
285 vassert(i == 16); in fitsIn8x4()
292 vassert(hregClass(src) == HRcInt32); in mk_iMOVds_RR()
293 vassert(hregClass(dst) == HRcInt32); in mk_iMOVds_RR()
390 vassert(ARM_N_ARGREGS == 4); in doHelperCall()
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Dhost_x86_defs.c61 vassert(r >= 0 && r < 8); in ppHRegX86()
66 vassert(r >= 0 && r < 6); in ppHRegX86()
71 vassert(r >= 0 && r < 8); in ppHRegX86()
175 vassert(shift >= 0 && shift <= 3); in X86AMode_IRRS()
579 vassert(op != Xalu_MUL); in X86Instr_Alu32M()
632 vassert(op == Xsh_SHL || op == Xsh_SHR); in X86Instr_Sh3232()
647 vassert(regparms >= 0 && regparms <= 3); in X86Instr_Call()
685 vassert(cond != Xcc_ALWAYS); in X86Instr_CMov32()
696 vassert(szSmall == 1 || szSmall == 2); in X86Instr_LoadEX()
705 vassert(sz == 1 || sz == 2); in X86Instr_Store()
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Dhost_ppc_isel.c298 vassert(tmp >= 0); in lookupIRTemp()
299 vassert(tmp < env->n_vregmap); in lookupIRTemp()
306 vassert(tmp >= 0); in lookupIRTempPair()
307 vassert(tmp < env->n_vregmap); in lookupIRTempPair()
308 vassert(env->vregmapMedLo[tmp] != INVALID_HREG); in lookupIRTempPair()
317 vassert(!env->mode64); in lookupIRTempQuad()
318 vassert(tmp >= 0); in lookupIRTempQuad()
319 vassert(tmp < env->n_vregmap); in lookupIRTempQuad()
320 vassert(env->vregmapMedLo[tmp] != INVALID_HREG); in lookupIRTempQuad()
474 vassert(hregClass(r_dst) == hregClass(r_src)); in mk_iMOVds_RR()
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Dguest_arm_toIR.c177 do { vassert(__curr_is_Thumb); } while (0)
180 do { vassert(! __curr_is_Thumb); } while (0)
211 vassert(sh >= 0 && sh < 32); in ROR32()
286 vassert(i < 256); in mkU8()
334 vassert(isPlausibleIRType(ty)); in newTemp()
348 vassert(rot >= 0 && rot < 32); in genROR32()
467 default: vassert(0); in integerGuestRegOffset()
474 vassert(iregNo < 16); in llGetIReg()
484 vassert(iregNo < 16); in getIRegA()
492 vassert(0 == (guest_R15_curr_instr_notENC & 3)); in getIRegA()
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Dguest_arm_helpers.c97 vassert( ((UInt)(_cc_op)) < ARMG_CC_OP_NUMBER); \
144 vassert((oldC & ~1) == 0); in armg_calculate_flag_n()
154 vassert((oldC & ~1) == 0); in armg_calculate_flag_n()
224 vassert((oldC & ~1) == 0); in armg_calculate_flag_z()
234 vassert((oldC & ~1) == 0); in armg_calculate_flag_z()
304 vassert((oldC & ~1) == 0); in armg_calculate_flag_c()
314 vassert((oldC & ~1) == 0); in armg_calculate_flag_c()
321 vassert((shco & ~1) == 0); in armg_calculate_flag_c()
328 vassert((cc_dep3 & ~3) == 0); in armg_calculate_flag_c()
335 vassert((cc_dep3 & ~3) == 0); in armg_calculate_flag_c()
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Dhost_arm_defs.c64 vassert(r >= 0 && r < 16); in ppHRegARM()
69 vassert(r >= 0 && r < 32); in ppHRegARM()
74 vassert(r >= 0 && r < 32); in ppHRegARM()
79 vassert(r >= 0 && r < 16); in ppHRegARM()
187 vassert(i == *nregs); in getAllocableRegs_ARM()
224 vassert(-4095 <= simm13 && simm13 <= 4095); in ARMAMode1_RI()
233 vassert(0 <= shift && shift <= 3); in ARMAMode1_RRS()
252 vassert(0); in ppARMAMode1()
292 vassert(-255 <= simm9 && simm9 <= 255); in ARMAMode2_RI()
318 vassert(0); in ppARMAMode2()
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Dhost_amd64_isel.c161 vassert(tmp >= 0); in lookupIRTemp()
162 vassert(tmp < env->n_vregmap); in lookupIRTemp()
169 vassert(tmp >= 0); in lookupIRTempPair()
170 vassert(tmp < env->n_vregmap); in lookupIRTempPair()
171 vassert(env->vregmapHI[tmp] != INVALID_HREG); in lookupIRTempPair()
304 vassert(hregClass(src) == HRcInt64); in mk_iMOVsd_RR()
305 vassert(hregClass(dst) == HRcInt64); in mk_iMOVsd_RR()
313 vassert(hregClass(src) == HRcVec128); in mk_vMOVsd_RR()
314 vassert(hregClass(dst) == HRcVec128); in mk_vMOVsd_RR()
322 vassert(n > 0 && n < 256 && (n%8) == 0); in add_to_rsp()
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Dguest_x86_toIR.c324 vassert(isPlausibleIRType(ty)); in newTemp()
455 vassert(archreg < 8); in integerGuestRegOffset()
458 vassert(!host_is_bigendian); in integerGuestRegOffset()
474 vassert(archreg >= 4 && archreg < 8 && sz == 1); in integerGuestRegOffset()
521 vassert(!host_is_bigendian); in xmmGuestRegLane16offset()
522 vassert(laneno >= 0 && laneno < 8); in xmmGuestRegLane16offset()
529 vassert(!host_is_bigendian); in xmmGuestRegLane32offset()
530 vassert(laneno >= 0 && laneno < 4); in xmmGuestRegLane32offset()
537 vassert(!host_is_bigendian); in xmmGuestRegLane64offset()
538 vassert(laneno >= 0 && laneno < 2); in xmmGuestRegLane64offset()
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Dhost_x86_isel.c195 vassert(tmp >= 0); in lookupIRTemp()
196 vassert(tmp < env->n_vregmap); in lookupIRTemp()
202 vassert(tmp >= 0); in lookupIRTemp64()
203 vassert(tmp < env->n_vregmap); in lookupIRTemp64()
204 vassert(env->vregmapHI[tmp] != INVALID_HREG); in lookupIRTemp64()
291 vassert(hregClass(src) == HRcInt32); in mk_iMOVsd_RR()
292 vassert(hregClass(dst) == HRcInt32); in mk_iMOVsd_RR()
301 vassert(hregClass(src) == HRcVec128); in mk_vMOVsd_RR()
302 vassert(hregClass(dst) == HRcVec128); in mk_vMOVsd_RR()
310 vassert(n > 0 && n < 256 && (n%4) == 0); in add_to_esp()
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Dir_match.h55 vassert(vexGetAllocMode() == VexAllocModeTEMP); \
59 vassert(vexGetAllocMode() == VexAllocModeTEMP); \
Dguest_generic_x87.c361 vassert(j >= 0 && j < 52); in convert_f80le_to_f64le()
633 vassert((pol >> 2) == 0); in compute_PCMPxSTRx_gen_output()
634 vassert((idx >> 1) == 0); in compute_PCMPxSTRx_gen_output()
701 vassert((pol >> 2) == 0); in compute_PCMPxSTRx_gen_output_wide()
702 vassert((idx >> 1) == 0); in compute_PCMPxSTRx_gen_output_wide()
790 vassert(imm8 < 0x80); in compute_PCMPxSTRx()
791 vassert((zmaskL >> 16) == 0); in compute_PCMPxSTRx()
792 vassert((zmaskR >> 16) == 0); in compute_PCMPxSTRx()
1041 vassert(imm8 < 0x80); in compute_PCMPxSTRx_wide()
1042 vassert((zmaskL >> 8) == 0); in compute_PCMPxSTRx_wide()
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Dhost_s390_disasm.c56 vassert(archreg < 16); in gpr_operand()
73 vassert(archreg < 16); in fpr_operand()
90 vassert(archreg < 16); in ar_operand()
142 vassert(vex_strlen(prefix) + vex_strlen(suffix) + sizeof mask_id[0] <= sizeof buf); in construct_mnemonic()
455 vassert(p < buf + sizeof buf); /* detect buffer overwrite */ in s390_disasm()
Dhost_s390_isel.c195 vassert(tmp < env->n_vregmap); in lookupIRTemp()
196 vassert(env->vregmap[tmp] != INVALID_HREG); in lookupIRTemp()
206 vassert(tmp < env->n_vregmap); in lookupIRTemp128()
207 vassert(env->vregmapHI[tmp] != INVALID_HREG); in lookupIRTemp128()
329 vassert(typeOfIRExpr(env->type_env, expr) == Ity_I64); in s390_isel_amode()
334 vassert(s390_amode_is_sane(am)); in s390_isel_amode()
612 vassert(ty == Ity_I128); in s390_isel_int128_expr_wrk()
756 vassert(hregIsVirtual(*dst_hi)); in s390_isel_int128_expr()
757 vassert(hregIsVirtual(*dst_lo)); in s390_isel_int128_expr()
758 vassert(hregClass(*dst_hi) == HRcInt64); in s390_isel_int128_expr()
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Dhost_generic_regs.c110 vassert(tab->n_used < N_HREG_USAGE); in addHRegUse()
171 vassert(map->n_used+1 < N_HREG_REMAP); in addToHRegRemap()
205 vassert(ha->arr_used <= ha->arr_size); in addHInstr()
Dguest_ppc_toIR.c396 vassert(4 == sizeof(UInt)); in float_to_bits()
397 vassert(4 == sizeof(Float)); in float_to_bits()
398 vassert(4 == sizeof(u)); in float_to_bits()
415 vassert(begin < 32); in MASK32()
416 vassert(end < 32); in MASK32()
427 vassert(begin < 64); in MASK64()
428 vassert(end < 64); in MASK64()
456 vassert(isPlausibleIRType(ty)); in newTemp()
518 vassert(tyA == Ity_I32 || tyA == Ity_I64); in storeBE()
570 vassert(i == 0 || i == 0xffff); in mkV128()
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