| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 77 unsigned RegClass = Desc.OpInfo[OpNo].RegClass; in isSrcOperand() local
78 return (AMDGPU::SSrc_32RegClassID == RegClass) || in isSrcOperand()
79 (AMDGPU::SSrc_64RegClassID == RegClass) || in isSrcOperand()
80 (AMDGPU::VSrc_32RegClassID == RegClass) || in isSrcOperand()
81 (AMDGPU::VSrc_64RegClassID == RegClass); in isSrcOperand()
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 596 static bool isVSrc(unsigned RegClass) { in isVSrc() argument
597 return AMDGPU::VSrc_32RegClassID == RegClass || in isVSrc()
598 AMDGPU::VSrc_64RegClassID == RegClass; in isVSrc()
602 static bool isSSrc(unsigned RegClass) { in isSSrc() argument
603 return AMDGPU::SSrc_32RegClassID == RegClass || in isSSrc()
604 AMDGPU::SSrc_64RegClassID == RegClass; in isSSrc()
696 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass; in getRegClassForNode()
730 unsigned RegClass) const { in fitsRegClass()
736 return TRI->getRegClass(RegClass)->hasSubClassEq(RC); in fitsRegClass()
741 unsigned RegClass, in ensureSRegLimit() argument
[all …]
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| D | SIISelLowering.h | 36 unsigned RegClass) const;
38 unsigned RegClass, bool &ScalarSlotUsed) const;
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| D | R600InstrInfo.cpp | 689 switch (MI->getDesc().OpInfo->RegClass) { in getBranchInstr()
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterScavenging.h | 125 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
154 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
156 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister() argument
157 return scavengeRegister(RegClass, MBBI, SPAdj); in scavengeRegister()
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| D | RegisterClassInfo.h | 46 OwningArrayPtr<RCInfo> RegClass; variable
72 const RCInfo &RCI = RegClass[RC->getID()]; in get()
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| D | MachineRegisterInfo.h | 340 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 35 const TargetRegisterClass &RegClass, in printModifiedFPRAsmOperand() argument
41 if (RegClass.contains(*AR)) { in printModifiedFPRAsmOperand()
53 const TargetRegisterClass &RegClass, in printModifiedGPRAsmOperand() argument
55 char Prefix = &RegClass == &AArch64::GPR32RegClass ? 'w' : 'x'; in printModifiedGPRAsmOperand()
67 if (RegClass.contains(*AR)) { in printModifiedGPRAsmOperand()
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| D | AArch64FrameLowering.h | 31 const TargetRegisterClass *RegClass; // E.g. GPR64RegClass member
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| D | AArch64FrameLowering.cpp | 452 if (PossClasses[ClassIdx].RegClass->contains(Reg)) in emitFrameMemOps()
457 const TargetRegisterClass &TheClass = *PossClasses[ClassIdx].RegClass; in emitFrameMemOps()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrArithmetic.td | 597 /// RegClass - This is the register class associated with this type. For
599 RegisterClass RegClass = regclass;
691 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
699 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
700 [(set typeinfo.RegClass:$dst,
701 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
710 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
717 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
718 [(set typeinfo.RegClass:$dst, EFLAGS,
719 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 101 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ in createVirtualRegister() argument
102 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
103 assert(RegClass->isAllocatable() && in createVirtualRegister()
109 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
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| D | RegisterClassInfo.cpp | 42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
79 RCInfo &RCI = RegClass[RC->getID()]; in compute()
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| D | TargetInstrInfo.cpp | 45 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
47 return TRI->getPointerRegClass(MF, RegClass); in getRegClass()
50 if (RegClass < 0) in getRegClass()
54 return TRI->getRegClass(RegClass); in getRegClass()
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 63 int16_t RegClass;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 432 SDValue RegClass = CurDAG->getTargetConstant(RCID, MVT::i32); in selectNode() local
435 const SDValue Ops[] = { RegClass, Node->getOperand(0), LoIdx, in selectNode()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1580 SDValue RegClass = in createGPRPairNode() local
1584 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
1591 SDValue RegClass = in createSRegPairNode() local
1595 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode()
1602 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32); in createDRegPairNode() local
1605 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode()
1612 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); in createQRegPairNode() local
1615 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode()
1623 SDValue RegClass = in createQuadSRegsNode() local
1629 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 846 if (UseInfo->RegClass /* Kind */ != 1) in FoldImmediate()
849 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID && in FoldImmediate()
850 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID) in FoldImmediate()
865 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in FoldImmediate()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | R600InstrInfo.cpp | 253 switch (MI->getDesc().OpInfo->RegClass) { in getBranchInstr()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600InstrInfo.cpp | 253 switch (MI->getDesc().OpInfo->RegClass) { in getBranchInstr()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 278 unsigned &RegClass, unsigned &Cost, in GetCostForDef() argument
291 RegClass = RC->getID(); in GetCostForDef()
300 RegClass = RC->getID(); in GetCostForDef()
308 RegClass = RC->getID(); in GetCostForDef()
313 RegClass = TLI->getRepRegClassFor(VT)->getID(); in GetCostForDef()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 179 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
900 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { in matchRegisterByNumber() argument
905 return getReg(RegClass, RegNum); in matchRegisterByNumber()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1261 CodeGenRegisterClass *RegClass = RegBank.getRegClasses()[i]; in computeUberSets() local
1262 if (!RegClass->Allocatable) in computeUberSets()
1265 const CodeGenRegister::Set &Regs = RegClass->getMembers(); in computeUberSets()
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| D | CodeGenDAGPatterns.cpp | 1341 Record *RegClass = R->getValueAsDef("RegClass"); in getImplicitType() local
1343 return EEVT::TypeSet(T.getRegisterClass(RegClass).getValueTypes()); in getImplicitType()
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| /external/llvm/include/llvm/Target/ |
| D | Target.td | 603 // RegClass - The register class of the operand.
604 RegisterClass RegClass = regclass;
|