| /external/llvm/lib/Target/X86/ |
| D | X86InstrCMovSetCC.td | 82 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
95 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
96 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
97 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
98 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
99 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
100 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
101 defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal
102 defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than
103 defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set
[all …]
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| D | X86TargetTransformInfo.cpp | 470 { ISD::SETCC, MVT::v2f64, 1 }, in getCmpSelInstrCost()
471 { ISD::SETCC, MVT::v4f32, 1 }, in getCmpSelInstrCost()
472 { ISD::SETCC, MVT::v2i64, 1 }, in getCmpSelInstrCost()
473 { ISD::SETCC, MVT::v4i32, 1 }, in getCmpSelInstrCost()
474 { ISD::SETCC, MVT::v8i16, 1 }, in getCmpSelInstrCost()
475 { ISD::SETCC, MVT::v16i8, 1 }, in getCmpSelInstrCost()
479 { ISD::SETCC, MVT::v4f64, 1 }, in getCmpSelInstrCost()
480 { ISD::SETCC, MVT::v8f32, 1 }, in getCmpSelInstrCost()
482 { ISD::SETCC, MVT::v4i64, 4 }, in getCmpSelInstrCost()
483 { ISD::SETCC, MVT::v8i32, 4 }, in getCmpSelInstrCost()
[all …]
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| D | X86ISelLowering.cpp | 517 setOperationAction(ISD::SETCC , MVT::i8 , Custom); in resetOperationActions()
518 setOperationAction(ISD::SETCC , MVT::i16 , Custom); in resetOperationActions()
519 setOperationAction(ISD::SETCC , MVT::i32 , Custom); in resetOperationActions()
520 setOperationAction(ISD::SETCC , MVT::f32 , Custom); in resetOperationActions()
521 setOperationAction(ISD::SETCC , MVT::f64 , Custom); in resetOperationActions()
522 setOperationAction(ISD::SETCC , MVT::f80 , Custom); in resetOperationActions()
525 setOperationAction(ISD::SETCC , MVT::i64 , Custom); in resetOperationActions()
846 setOperationAction(ISD::SETCC, VT, Expand); in resetOperationActions()
956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); in resetOperationActions()
957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); in resetOperationActions()
[all …]
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| D | X86ISelLowering.h | 95 SETCC, enumerator
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | SIISelLowering.cpp | 62 setTargetDAGCombine(ISD::SETCC); in SITargetLowering()
318 ISD::SETCC, in LowerBR_CC()
384 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC); in LowerSELECT_CC()
409 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0), in PerformDAGCombine()
415 case ISD::SETCC: { in PerformDAGCombine()
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| D | R600ISelLowering.cpp | 48 setOperationAction(ISD::SETCC, MVT::i32, Custom); in R600TargetLowering()
252 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIISelLowering.cpp | 62 setTargetDAGCombine(ISD::SETCC); in SITargetLowering()
318 ISD::SETCC, in LowerBR_CC()
384 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC); in LowerSELECT_CC()
409 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0), in PerformDAGCombine()
415 case ISD::SETCC: { in PerformDAGCombine()
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| D | R600ISelLowering.cpp | 48 setOperationAction(ISD::SETCC, MVT::i32, Custom); in R600TargetLowering()
252 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 114 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AArch64TargetLowering()
115 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AArch64TargetLowering()
116 setOperationAction(ISD::SETCC, MVT::f32, Custom); in AArch64TargetLowering()
117 setOperationAction(ISD::SETCC, MVT::f64, Custom); in AArch64TargetLowering()
232 setOperationAction(ISD::SETCC, MVT::f128, Custom); in AArch64TargetLowering()
285 setOperationAction(ISD::SETCC, MVT::v8i8, Custom); in AArch64TargetLowering()
286 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); in AArch64TargetLowering()
287 setOperationAction(ISD::SETCC, MVT::v4i16, Custom); in AArch64TargetLowering()
288 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); in AArch64TargetLowering()
289 setOperationAction(ISD::SETCC, MVT::v2i32, Custom); in AArch64TargetLowering()
[all …]
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| D | AArch64ISelLowering.h | 81 SETCC, enumerator
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 78 setOperationAction(ISD::SETCC, MVT::v2i1, Expand); in SITargetLowering()
79 setOperationAction(ISD::SETCC, MVT::v4i1, Expand); in SITargetLowering()
92 setTargetDAGCombine(ISD::SETCC); in SITargetLowering()
431 if (Intr->getOpcode() == ISD::SETCC) { in LowerBRCOND()
513 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC); in LowerSELECT_CC()
566 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0), in PerformDAGCombine()
572 case ISD::SETCC: { in PerformDAGCombine()
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| D | R600ISelLowering.cpp | 53 setOperationAction(ISD::SETCC, MVT::v4i32, Expand); in R600TargetLowering()
54 setOperationAction(ISD::SETCC, MVT::v2i32, Expand); in R600TargetLowering()
68 setOperationAction(ISD::SETCC, MVT::i32, Expand); in R600TargetLowering()
69 setOperationAction(ISD::SETCC, MVT::f32, Expand); in R600TargetLowering()
771 ISD::SETCC, in LowerFPTOUINT()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 339 SETCC, enumerator
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 32 SETCC, enumerator
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 52 SETCC, enumerator
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| D | MSP430ISelLowering.cpp | 112 setOperationAction(ISD::SETCC, MVT::i8, Custom); in MSP430TargetLowering()
113 setOperationAction(ISD::SETCC, MVT::i16, Custom); in MSP430TargetLowering()
196 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; in ScalarizeVectorResult()
310 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); in ScalarizeVecRes_SETCC()
337 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, in ScalarizeVecRes_VSETCC()
513 case ISD::SETCC: in SplitVectorResult()
1055 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; in SplitVectorOperand()
1381 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); in SplitVecOp_VSETCC()
1382 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); in SplitVecOp_VSETCC()
1444 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; in WidenVectorResult()
2174 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT, in WidenVecRes_SETCC()
2229 return DAG.getNode(ISD::SETCC, SDLoc(N), in WidenVecRes_VSETCC()
[all …]
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| D | LegalizeVectorOps.cpp | 221 case ISD::SETCC: in LegalizeOp()
296 else if (Node->getOpcode() == ISD::SETCC) in LegalizeOp()
761 Ops[i] = DAG.getNode(ISD::SETCC, dl, in UnrollVSETCC()
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| D | TargetLowering.cpp | 190 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, in softenSetCCOperands()
194 NewLHS = DAG.getNode(ISD::SETCC, dl, in softenSetCCOperands()
1168 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { in SimplifySetCC()
1273 (isOperationLegal(ISD::SETCC, newVT) && in SimplifySetCC()
1316 if (N0.getOpcode() == ISD::SETCC && in SimplifySetCC()
1364 Op0.getOperand(0).getOpcode() == ISD::SETCC && in SimplifySetCC()
1365 Op0.getOperand(1).getOpcode() == ISD::SETCC) { in SimplifySetCC()
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| D | DAGCombiner.cpp | 556 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
1141 case ISD::SETCC: return visitSETCC(N); in visit()
2689 TLI.isOperationLegal(ISD::SETCC, in visitAND()
3201 TLI.isOperationLegal(ISD::SETCC, in visitOR()
3462 case ISD::SETCC: in visitXOR()
4204 if (N0.getOpcode() == ISD::SETCC) { in visitSELECT()
4231 if (N0.getOpcode() == ISD::SETCC) { in visitVSELECT()
4286 if (SCC.getOpcode() == ISD::SETCC) in visitSELECT_CC()
4325 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
4387 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), in ExtendSetCCUses()
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| D | LegalizeDAG.cpp | 1190 case ISD::SETCC: in LegalizeOp()
1193 Node->getOpcode() == ISD::SETCC ? 2 : 1; in LegalizeOp()
3546 if (Tmp1.getOpcode() == ISD::SETCC) { in ExpandNode()
3593 if (Tmp2.getOpcode() == ISD::SETCC) { in ExpandNode()
3610 case ISD::SETCC: { in ExpandNode()
3730 Node->getOpcode() == ISD::SETCC) { in PromoteNode()
3870 case ISD::SETCC: { in PromoteNode()
3879 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), in PromoteNode()
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| D | SelectionDAGDumper.cpp | 184 case ISD::SETCC: return "setcc"; in getOperationName()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 73 setTargetDAGCombine(ISD::SETCC); in MipsSETargetLowering()
511 case ISD::SETCC: { in PerformDAGCombine()
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| D | MipsISelLowering.cpp | 238 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); in MipsTargetLowering()
252 setOperationAction(ISD::SETCC, MVT::f32, Custom); in MipsTargetLowering()
253 setOperationAction(ISD::SETCC, MVT::f64, Custom); in MipsTargetLowering()
500 if (Op.getOpcode() != ISD::SETCC) in createFPCmp()
538 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
738 case ISD::SETCC: return lowerSETCC(Op, DAG); in LowerOperation()
1467 SDValue Cond = DAG.getNode(ISD::SETCC, DL, in lowerSELECT_CC()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1289 setOperationAction(ISD::SETCC, MVT::i32, Expand); in SparcTargetLowering()
1290 setOperationAction(ISD::SETCC, MVT::f32, Expand); in SparcTargetLowering()
1291 setOperationAction(ISD::SETCC, MVT::f64, Expand); in SparcTargetLowering()
1309 setOperationAction(ISD::SETCC, MVT::i64, Expand); in SparcTargetLowering()
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