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Searched refs:isAllocatable (Results 1 – 21 of 21) sorted by relevance

/external/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp80 if (!RC || RC->isAllocatable()) in getAllocatableClass()
90 if (SubRC->isAllocatable()) in getAllocatableClass()
124 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); in getAllocatableSetForRC()
141 if ((*I)->isAllocatable()) in getAllocatableSet()
DMachineRegisterInfo.cpp44 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); in setRegClass()
103 assert(RegClass->isAllocatable() && in createVirtualRegister()
416 if (!def_empty(*AI) || isAllocatable(*AI)) in isConstantPhysReg()
DCalcSpillWeights.cpp170 if (hweight > bestPhys && mri.isAllocatable(hint)) in CalculateWeightAndHint()
DRegAllocFast.cpp519 !RC->contains(Hint) || !MRI->isAllocatable(Hint))) in allocVirtReg()
793 if (MRI->isAllocatable(*I)) in AllocateBasicBlock()
926 if (!MRI->isAllocatable(Reg)) continue; in AllocateBasicBlock()
1015 if (!MRI->isAllocatable(Reg)) continue; in AllocateBasicBlock()
DAggressiveAntiDepBreaker.cpp621 if (!MRI.isAllocatable(NewSuperReg)) continue; in FindSuitableFreeRegisters()
804 if (!MRI.isAllocatable(AntiDepReg)) { in BreakAntiDependencies()
DMachineVerifier.cpp188 bool isAllocatable(unsigned Reg) { in isAllocatable() function
189 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg); in isAllocatable()
505 if (isAllocatable(reg) && !MBB->isLandingPad() && in visitMachineBasicBlockBefore()
DCriticalAntiDepBreaker.cpp524 if (!MRI.isAllocatable(AntiDepReg)) in BreakAntiDependencies()
DRegAllocPBQP.cpp356 if (!mf->getRegInfo().isAllocatable(dst)) { in build()
DMachineCSE.cpp261 if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i])) in PhysRegDefsReach()
DRegisterPressure.cpp379 else if (MRI->isAllocatable(Reg)) { in pushRegUnits()
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td58 let isAllocatable = 0;
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h100 bool isAllocatable() const { return MC->isAllocatable(); } in isAllocatable() function
DTarget.td190 // isAllocatable - Specify that the register class can be used for virtual
192 // model instruction operand constraints, and should have isAllocatable = 0.
193 bit isAllocatable = 1;
/external/llvm/lib/Target/R600/
DR600RegisterInfo.td128 let isAllocatable = 0 in {
133 } // End isAllocatable = 0
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td227 let isAllocatable = 0;
230 let isAllocatable = 0;
/external/llvm/include/llvm/MC/
DMCRegisterInfo.h99 bool isAllocatable() const { return Allocatable; } in isAllocatable() function
/external/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h476 bool isAllocatable(unsigned PhysReg) const { in isAllocatable() function
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td431 let isAllocatable = 0;
444 let isAllocatable = 0;
448 let isAllocatable = 0;
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td202 let isAllocatable = 0;
/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td27 bit isAllocatable = 0;
/external/llvm/lib/Target/ARM/
DARMRegisterInfo.td264 let isAllocatable = 0;