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Searched refs:RegStorage (Results 1 – 25 of 47) sorted by relevance

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/art/compiler/dex/quick/mips/
Dmips_lir.h119 #define rMIPS_LR RegStorage::kInvalidRegVal
120 #define rMIPS_PC RegStorage::kInvalidRegVal
146 rZERO = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 0,
147 rAT = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1,
148 rV0 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 2,
149 rV1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 3,
150 rA0 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 4,
151 rA1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 5,
152 rA2 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 6,
153 rA3 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 7,
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Dcodegen_mips.h34 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
37 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
39 LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
40 LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
43 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
45 LIR* GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest);
46 LIR* GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src);
47 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg);
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Dtarget_mips.cc29 static constexpr RegStorage core_regs_arr[] =
33 static constexpr RegStorage sp_regs_arr[] =
36 static constexpr RegStorage dp_regs_arr[] =
38 static constexpr RegStorage reserved_regs_arr[] =
40 static constexpr RegStorage core_temps_arr[] =
43 static constexpr RegStorage sp_temps_arr[] =
46 static constexpr RegStorage dp_temps_arr[] =
49 static constexpr ArrayRef<const RegStorage> empty_pool;
50 static constexpr ArrayRef<const RegStorage> core_regs(core_regs_arr);
51 static constexpr ArrayRef<const RegStorage> sp_regs(sp_regs_arr);
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Dutility_mips.cc25 LIR* MipsMir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { in OpFpRegCopy()
37 RegStorage t_opnd = r_src; in OpFpRegCopy()
79 LIR* MipsMir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { in LoadConstantNoClobber()
82 RegStorage r_dest_save = r_dest; in LoadConstantNoClobber()
116 LIR* MipsMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg()
131 LIR* MipsMir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { in OpRegImm()
151 RegStorage r_scratch = AllocTemp(); in OpRegImm()
161 LIR* MipsMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) { in OpRegRegReg()
202 LIR* MipsMir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) { in OpRegRegImm()
277 RegStorage r_scratch = AllocTemp(); in OpRegRegImm()
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Dint_mips.cc48 RegStorage t0 = AllocTemp(); in GenCmpLong()
49 RegStorage t1 = AllocTemp(); in GenCmpLong()
65 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
118 RegStorage t_reg = AllocTemp(); in OpCmpBranch()
131 LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { in OpCmpImmBranch()
135 RegStorage t_reg = AllocTemp(); in OpCmpImmBranch()
152 RegStorage t_reg = AllocTemp(); in OpCmpImmBranch()
163 LIR* MipsMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { in OpRegCopyNoInsert()
181 void MipsMir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { in OpRegCopy()
188 void MipsMir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { in OpRegCopyWide()
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Dcall_mips.cc85 RegStorage r_end = AllocTemp(); in GenLargeSparseSwitch()
104 RegStorage r_base = AllocTemp(); in GenLargeSparseSwitch()
112 RegStorage r_key = AllocTemp(); in GenLargeSparseSwitch()
118 RegStorage r_disp = AllocTemp(); in GenLargeSparseSwitch()
162 RegStorage r_key; in GenLargePackedSwitch()
197 RegStorage r_base = AllocTemp(); in GenLargePackedSwitch()
201 RegStorage r_disp = AllocTemp(); in GenLargePackedSwitch()
246 RegStorage r_tgt = LoadHelper(kQuickHandleFillArrayData); in GenFillArrayData()
264 RegStorage reset_reg = AllocTempRef(); in GenMoveException()
275 void MipsMir2Lir::MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) { in MarkGCCard()
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/art/compiler/dex/quick/arm/
Darm_lir.h113 r0 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 0,
114 r1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1,
115 r2 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 2,
116 r3 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 3,
118 rARM_SUSPEND = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 4,
120 r4 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 4,
122 r5 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 5,
123 r6 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 6,
124 r7 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 7,
125 r8 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 8,
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Dcodegen_arm.h34 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
37 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
39 LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
40 LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
43 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
45 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg);
48 RegStorage TargetReg(SpecialTargetRegister reg);
49 RegStorage GetArgMappingToPhysicalReg(int arg_num);
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Dtarget_arm.cc29 static constexpr RegStorage core_regs_arr[] =
33 static constexpr RegStorage core_regs_arr[] =
37 static constexpr RegStorage sp_regs_arr[] =
42 static constexpr RegStorage dp_regs_arr[] =
46 static constexpr RegStorage reserved_regs_arr[] =
48 static constexpr RegStorage core_temps_arr[] = {rs_r0, rs_r1, rs_r2, rs_r3, rs_r12};
50 static constexpr RegStorage reserved_regs_arr[] =
52 static constexpr RegStorage core_temps_arr[] = {rs_r0, rs_r1, rs_r2, rs_r3, rs_r4, rs_r12};
54 static constexpr RegStorage sp_temps_arr[] =
57 static constexpr RegStorage dp_temps_arr[] =
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Dutility_arm.cc73 DCHECK(RegStorage::IsSingle(r_dest)); in LoadFPConstantValue()
173 LIR* ArmMir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { in LoadConstantNoClobber()
223 LIR* ArmMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg()
238 LIR* ArmMir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, in OpRegRegShift()
371 LIR* ArmMir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { in OpRegReg()
375 LIR* ArmMir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) { in OpMovRegMem()
380 LIR* ArmMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { in OpMovMemReg()
385 LIR* ArmMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg()
390 LIR* ArmMir2Lir::OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, in OpRegRegRegShift()
391 RegStorage r_src2, int shift) { in OpRegRegRegShift()
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/art/compiler/dex/quick/x86/
Dx86_lir.h118 r0 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 0,
119 r0q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 0,
121 r1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1,
122 r1q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 1,
124 r2 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 2,
125 r2q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 2,
127 r3 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 3,
128 r3q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 3,
130 r4sp_32 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 4,
132 r4sp_64 = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 4,
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Dcodegen_x86.h31 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0;
39 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref);
54 RegStorage Get(int in_position);
57 std::map<int, RegStorage> mapping_;
71 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
72 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
74 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
76 LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
77 LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
78 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
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Dtarget_x86.cc30 static constexpr RegStorage core_regs_arr_32[] = {
33 static constexpr RegStorage core_regs_arr_64[] = {
37 static constexpr RegStorage core_regs_arr_64q[] = {
41 static constexpr RegStorage sp_regs_arr_32[] = {
44 static constexpr RegStorage sp_regs_arr_64[] = {
48 static constexpr RegStorage dp_regs_arr_32[] = {
51 static constexpr RegStorage dp_regs_arr_64[] = {
55 static constexpr RegStorage xp_regs_arr_32[] = {
58 static constexpr RegStorage xp_regs_arr_64[] = {
62 static constexpr RegStorage reserved_regs_arr_32[] = {rs_rX86_SP_32};
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Dutility_x86.cc29 LIR* X86Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { in OpFpRegCopy()
81 LIR* X86Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { in LoadConstantNoClobber()
82 RegStorage r_dest_save = r_dest; in LoadConstantNoClobber()
120 LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg()
133 LIR* X86Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { in OpRegImm()
195 LIR* X86Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { in OpRegReg()
251 LIR* X86Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) { in OpMovRegMem()
303 LIR* X86Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { in OpMovMemReg()
356 LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg()
364 LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) { in OpRegMem()
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Dcall_x86.cc83 RegStorage start_of_method_reg; in GenLargePackedSwitch()
100 RegStorage keyReg; in GenLargePackedSwitch()
113 RegStorage disp_reg = AllocTemp(); in GenLargePackedSwitch()
152 RegStorage array_ptr = TargetReg(kArg0, kRef); in GenFillArrayData()
153 RegStorage payload = TargetPtrReg(kArg1); in GenFillArrayData()
154 RegStorage method_start = TargetPtrReg(kArg2); in GenFillArrayData()
188 void X86Mir2Lir::MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) { in MarkGCCard()
191 RegStorage reg_card_base = AllocTempRef(); in MarkGCCard()
192 RegStorage reg_card_no = AllocTempRef(); in MarkGCCard()
256 m2l_->CallHelper(RegStorage::InvalidReg(), kQuickThrowStackOverflow, in GenEntrySequence()
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/art/compiler/dex/quick/arm64/
Dcodegen_arm64.h32 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0;
40 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref);
53 RegStorage Get(int in_position);
56 std::map<int, RegStorage> mapping_;
74 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
75 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
77 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest,
79 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
81 LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale)
83 LIR* LoadConstantNoClobber(RegStorage r_dest, int value) OVERRIDE;
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Darm64_lir.h132 rw##nr = RegStorage::k32BitSolo | RegStorage::kCoreRegister | nr, \
133 rx##nr = RegStorage::k64BitSolo | RegStorage::kCoreRegister | nr, \
134 rf##nr = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | nr, \
135 rd##nr = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | nr,
139 rxzr = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 0x3f,
140 rwzr = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 0x3f,
163 constexpr RegStorage rs_w##nr(RegStorage::kValid | rw##nr); \
164 constexpr RegStorage rs_x##nr(RegStorage::kValid | rx##nr); \
165 constexpr RegStorage rs_f##nr(RegStorage::kValid | rf##nr); \
166 constexpr RegStorage rs_d##nr(RegStorage::kValid | rd##nr);
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Dtarget_arm64.cc29 static constexpr RegStorage core_regs_arr[] =
35 static constexpr RegStorage core64_regs_arr[] =
41 static constexpr RegStorage sp_regs_arr[] =
46 static constexpr RegStorage dp_regs_arr[] =
53 static constexpr RegStorage reserved_regs_arr[] =
55 static constexpr RegStorage reserved64_regs_arr[] =
57 static constexpr RegStorage core_temps_arr[] =
61 static constexpr RegStorage core64_temps_arr[] =
65 static constexpr RegStorage sp_temps_arr[] =
69 static constexpr RegStorage dp_temps_arr[] =
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Dutility_arm64.cc110 LIR* Arm64Mir2Lir::LoadFPConstantValue(RegStorage r_dest, int32_t value) { in LoadFPConstantValue()
134 LIR* Arm64Mir2Lir::LoadFPConstantValueWide(RegStorage r_dest, int64_t value) { in LoadFPConstantValueWide()
392 LIR* Arm64Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { in LoadConstantNoClobber()
456 LIR* Arm64Mir2Lir::LoadConstantWide(RegStorage r_dest, int64_t value) { in LoadConstantWide()
550 LIR* Arm64Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg()
566 LIR* Arm64Mir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift) { in OpRegRegShift()
634 LIR* Arm64Mir2Lir::OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, in OpRegRegExtend()
669 LIR* Arm64Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { in OpRegReg()
680 LIR* Arm64Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type… in OpMovRegMem()
685 LIR* Arm64Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type)… in OpMovMemReg()
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Dint_arm64.cc29 LIR* Arm64Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
92 RegStorage rs_dest, int result_reg_class) { in GenSelect()
104 RegStorage left_op = RegStorage::InvalidReg(); // The operands. in GenSelect()
105 RegStorage right_op = RegStorage::InvalidReg(); // The operands. in GenSelect()
109 RegStorage zero_reg = is_wide ? rs_xzr : rs_wzr; in GenSelect()
139 RegStorage t_reg2 = AllocTypedTemp(false, result_reg_class); in GenSelect()
175 void Arm64Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32()
176 int32_t true_val, int32_t false_val, RegStorage rs_dest, in GenSelectConst32()
259 LIR* Arm64Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, in OpCmpImmBranch()
287 LIR* Arm64Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, in OpCmpMemImmBranch()
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/art/compiler/dex/quick/
Dmir_to_lir.h341 RegisterInfo(RegStorage r, const ResourceMask& mask = kEncodeAll);
375 RegStorage GetReg() { return reg_; } in GetReg()
376 void SetReg(RegStorage reg) { reg_ = reg; } in SetReg()
389 RegStorage Partner() { return partner_; } in Partner()
390 void SetPartner(RegStorage partner) { partner_ = partner; } in SetPartner()
424 RegStorage reg_;
429 RegStorage partner_; // If wide_value, other reg of pair or self if 64-bit register.
444 const ArrayRef<const RegStorage>& core_regs,
445 const ArrayRef<const RegStorage>& core64_regs,
446 const ArrayRef<const RegStorage>& sp_regs,
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Dralloc_util.cc41 Mir2Lir::RegisterInfo::RegisterInfo(RegStorage r, const ResourceMask& mask) in RegisterInfo()
59 const ArrayRef<const RegStorage>& core_regs, in RegisterPool()
60 const ArrayRef<const RegStorage>& core64_regs, in RegisterPool()
61 const ArrayRef<const RegStorage>& sp_regs, in RegisterPool()
62 const ArrayRef<const RegStorage>& dp_regs, in RegisterPool()
63 const ArrayRef<const RegStorage>& reserved_regs, in RegisterPool()
64 const ArrayRef<const RegStorage>& reserved64_regs, in RegisterPool()
65 const ArrayRef<const RegStorage>& core_temps, in RegisterPool()
66 const ArrayRef<const RegStorage>& core64_temps, in RegisterPool()
67 const ArrayRef<const RegStorage>& sp_temps, in RegisterPool()
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Dlocal_optimizations.cc70 void Mir2Lir::ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src) { in ConvertMemOpIntoMove()
93 DCHECK(RegStorage::SameRegType(lir->operands[0], reg_id)); in EliminateLoad()
94 RegStorage dest_reg, src_reg; in EliminateLoad()
103 switch (reg_id & RegStorage::kShapeTypeMask) { in EliminateLoad()
104 case RegStorage::k32BitSolo | RegStorage::kCoreRegister: in EliminateLoad()
105 dest_reg = RegStorage::Solo32(lir->operands[0]); in EliminateLoad()
106 src_reg = RegStorage::Solo32(reg_id); in EliminateLoad()
108 case RegStorage::k64BitSolo | RegStorage::kCoreRegister: in EliminateLoad()
109 dest_reg = RegStorage::Solo64(lir->operands[0]); in EliminateLoad()
110 src_reg = RegStorage::Solo64(reg_id); in EliminateLoad()
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/art/compiler/dex/
Dreg_storage.h75 class RegStorage {
107 constexpr RegStorage(RegStorageKind rs_kind, int reg) in RegStorage() function
113 constexpr RegStorage(RegStorageKind rs_kind, int low_reg, int high_reg) in RegStorage() function
123 constexpr explicit RegStorage(uint16_t val) : reg_(val) {} in RegStorage() function
124 RegStorage() : reg_(kInvalid) {} in RegStorage() function
133 bool ExactlyEquals(const RegStorage& rhs) const { in ExactlyEquals()
137 bool NotExactlyEquals(const RegStorage& rhs) const { in NotExactlyEquals()
233 RegStorage GetLow() const { in GetLow()
235 return RegStorage(k32BitSolo, reg_ & kRegTypeMask); in GetLow()
245 RegStorage GetHigh() const { in GetHigh()
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Dreg_storage_eq.h28 inline bool operator==(const RegStorage& lhs, const RegStorage& rhs) {
32 inline bool operator!=(const RegStorage& lhs, const RegStorage& rhs) {

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