| /external/valgrind/main/ |
| D | glibc-2.2.supp | 21 # Cond (previously known as Value0)
29 Memcheck:Cond
35 Memcheck:Cond
42 Memcheck:Cond
51 elf_dynamic_do_rel.7/_dl_relocate_object_internal/dl_open_worker(Cond)
52 Memcheck:Cond
61 _dl_relocate_object*/*libc-2.2.?.so/_dl_catch_error*(Cond)
62 Memcheck:Cond
69 Memcheck:Cond
74 Memcheck:Cond
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| D | glibc-2.3.supp | 21 # Cond (previously known as Value0)
28 Memcheck:Cond
34 Memcheck:Cond
41 Memcheck:Cond
47 strlen/*dl_map_object*(Cond)
48 Memcheck:Cond
54 strlen/*dl_open_worker*(Cond)
55 Memcheck:Cond
61 Memcheck:Cond
81 Memcheck:Cond
[all …]
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| D | darwin11.supp | 18 Memcheck:Cond
30 Memcheck:Cond
39 Memcheck:Cond
57 Memcheck:Cond
64 Memcheck:Cond
80 Memcheck:Cond
94 Memcheck:Cond
109 Memcheck:Cond
117 Memcheck:Cond
130 Memcheck:Cond
[all …]
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| D | xfree-4.supp | 25 # Cond (previously known as Value0)
41 libX11.so.6.2/libX11.so.6.2/libX11.so.6.2(Cond)
42 Memcheck:Cond
49 libXt.so.6.2/libXt.so.6.2/libXt.so.6.2(Cond)
50 Memcheck:Cond
58 libXaw.so.7.0/libXaw.so.7.0/libXaw.so.7.0(Cond)
59 Memcheck:Cond
66 libXmu.so.6.2/libXmu.so.6.2/libXmu.so.6.2(Cond)
67 Memcheck:Cond
74 libXt.so.6.0/libXt.so.6.0/libXaw.so.7.0(Cond)
[all …]
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| D | darwin9.supp | 54 macos-Cond-1
55 Memcheck:Cond
62 macos-Cond-2
63 Memcheck:Cond
70 macos-Cond-3
71 Memcheck:Cond
78 macos-Cond-4
79 Memcheck:Cond
86 macos-Cond-5
87 Memcheck:Cond
[all …]
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| D | darwin12.supp | 7 Memcheck:Cond
33 Memcheck:Cond
41 Memcheck:Cond
65 Memcheck:Cond
73 Memcheck:Cond
91 Memcheck:Cond
109 Memcheck:Cond
134 Memcheck:Cond
142 Memcheck:Cond
150 Memcheck:Cond
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 73 SmallVectorImpl<MachineOperand> &Cond) const { in AnalyzeCondBr()
80 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
83 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
89 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
92 BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); in AnalyzeBranch()
99 const SmallVectorImpl<MachineOperand>& Cond) in BuildCondBr()
101 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
105 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
106 if (Cond[i].isReg()) in BuildCondBr()
107 MIB.addReg(Cond[i].getReg()); in BuildCondBr()
[all …]
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| D | MipsInstrInfo.h | 56 SmallVectorImpl<MachineOperand> &Cond,
63 const SmallVectorImpl<MachineOperand> &Cond,
67 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
71 SmallVectorImpl<MachineOperand> &Cond,
136 SmallVectorImpl<MachineOperand> &Cond) const;
139 const SmallVectorImpl<MachineOperand>& Cond) const;
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| /external/clang/test/SemaCXX/ |
| D | vector.cpp | 40 void conditional(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, in conditional() argument
43 __typeof__(Cond? c16 : c16) *c16p1 = &c16; in conditional()
44 __typeof__(Cond? ll16 : ll16) *ll16p1 = &ll16; in conditional()
45 __typeof__(Cond? c16e : c16e) *c16ep1 = &c16e; in conditional()
46 __typeof__(Cond? ll16e : ll16e) *ll16ep1 = &ll16e; in conditional()
49 __typeof__(Cond? c16 : c16e) *c16ep2 = &c16e; in conditional()
50 __typeof__(Cond? c16e : c16) *c16ep3 = &c16e; in conditional()
51 __typeof__(Cond? ll16 : ll16e) *ll16ep2 = &ll16e; in conditional()
52 __typeof__(Cond? ll16e : ll16) *ll16ep3 = &ll16e; in conditional()
55 (void)(Cond? c16 : ll16); in conditional()
[all …]
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 130 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in ReverseBranchCondition()
131 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in ReverseBranchCondition()
133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in ReverseBranchCondition()
157 Cond[0].setImm(CC); in ReverseBranchCondition()
175 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
210 Cond.clear(); in AnalyzeBranch()
234 if (Cond.empty()) { in AnalyzeBranch()
237 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
243 assert(Cond.size() == 1); in AnalyzeBranch()
251 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in AnalyzeBranch()
[all …]
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 196 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
229 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
230 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
251 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
252 Cond.push_back(SecondLastInst->getOperand(0)); in AnalyzeBranch()
284 const SmallVectorImpl<MachineOperand> &Cond, in InsertBranch() argument
288 assert((Cond.size() == 2 || Cond.size() == 0) && in InsertBranch()
292 if (Cond.empty()) { in InsertBranch()
297 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
298 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in InsertBranch()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| D | radeon_emulate_loops.c | 199 if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[0].File, in try_unroll_loop()
200 loop->Cond->U.I.SrcReg[0].Index)){ in try_unroll_loop()
201 limit = &loop->Cond->U.I.SrcReg[0]; in try_unroll_loop()
202 counter = &loop->Cond->U.I.SrcReg[1]; in try_unroll_loop()
204 else if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[1].File, in try_unroll_loop()
205 loop->Cond->U.I.SrcReg[1].Index)){ in try_unroll_loop()
206 limit = &loop->Cond->U.I.SrcReg[1]; in try_unroll_loop()
207 counter = &loop->Cond->U.I.SrcReg[0]; in try_unroll_loop()
285 switch(loop->Cond->U.I.Opcode){ in try_unroll_loop()
309 rc_remove_instruction(loop->Cond); in try_unroll_loop()
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_emulate_loops.c | 199 if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[0].File, in try_unroll_loop()
200 loop->Cond->U.I.SrcReg[0].Index)){ in try_unroll_loop()
201 limit = &loop->Cond->U.I.SrcReg[0]; in try_unroll_loop()
202 counter = &loop->Cond->U.I.SrcReg[1]; in try_unroll_loop()
204 else if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[1].File, in try_unroll_loop()
205 loop->Cond->U.I.SrcReg[1].Index)){ in try_unroll_loop()
206 limit = &loop->Cond->U.I.SrcReg[1]; in try_unroll_loop()
207 counter = &loop->Cond->U.I.SrcReg[0]; in try_unroll_loop()
285 switch(loop->Cond->U.I.Opcode){ in try_unroll_loop()
309 rc_remove_instruction(loop->Cond); in try_unroll_loop()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 1207 ISD::CondCode Cond, bool foldBooleans, in SimplifySetCC() argument
1212 switch (Cond) { in SimplifySetCC()
1227 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond); in SimplifySetCC()
1244 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1246 if ((C1 == 0) == (Cond == ISD::SETEQ)) { in SimplifySetCC()
1249 Cond = ISD::SETNE; in SimplifySetCC()
1253 Cond = ISD::SETEQ; in SimplifySetCC()
1257 Zero, Cond); in SimplifySetCC()
1274 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1278 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
[all …]
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| /external/llvm/test/Transforms/InstCombine/ |
| D | udiv_select_to_select_shift.ll | 2 ; udiv X, (Select Cond, C1, C2) --> Select Cond, (shr X, C1), (shr X, C2)
9 define i64 @test(i64 %X, i1 %Cond ) {
11 %divisor1 = select i1 %Cond, i64 16, i64 8
13 %divisor2 = select i1 %Cond, i64 8, i64 0
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| D | store.ll | 28 br i1 %C, label %Cond, label %Cond2
30 Cond:
44 ; CHECK-NEXT: %storemerge = phi i32 [ 47, %Cond2 ], [ -987654321, %Cond ]
52 br i1 %C, label %Cond, label %Cont
54 Cond:
64 ; CHECK-NEXT: %storemerge = phi i32 [ -987654321, %Cond ], [ 47, %0 ]
71 br i1 %C, label %Cond, label %Cont
73 Cond:
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| /external/clang/test/SemaTemplate/ |
| D | value-dependent-null-pointer-constant.cpp | 5 const char *f0(bool Cond) { in f0()
6 return Cond? "honk" : N; in f0()
9 const char *f1(bool Cond) { in f1()
10 return Cond? N : "honk"; in f1()
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| /external/clang/lib/StaticAnalyzer/Core/ |
| D | SimpleConstraintManager.cpp | 69 DefinedSVal Cond, in assume() argument
72 if (Optional<Loc> LV = Cond.getAs<Loc>()) { in assume()
81 Cond = SVB.evalCast(*LV, SVB.getContext().BoolTy, T).castAs<DefinedSVal>(); in assume()
84 return assume(state, Cond.castAs<NonLoc>(), Assumption); in assume()
115 NonLoc Cond, in assumeAux() argument
120 if (!canReasonAbout(Cond)) { in assumeAux()
122 SymbolRef sym = Cond.getAsSymExpr(); in assumeAux()
126 switch (Cond.getSubKind()) { in assumeAux()
131 nonloc::SymbolVal SV = Cond.castAs<nonloc::SymbolVal>(); in assumeAux()
182 bool b = Cond.castAs<nonloc::ConcreteInt>().getValue() != 0; in assumeAux()
[all …]
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| /external/llvm/test/Transforms/ADCE/ |
| D | 2003-11-16-MissingPostDominanceInfo.ll | 6 br i1 %C, label %Cond, label %Done
8 Cond: ; preds = %0
11 Loop: ; preds = %Loop, %Cond
15 Done: ; preds = %Cond, %0
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600InstrInfo.cpp | 180 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
216 Cond.push_back(predSet->getOperand(1)); in AnalyzeBranch()
217 Cond.push_back(predSet->getOperand(2)); in AnalyzeBranch()
218 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); in AnalyzeBranch()
240 Cond.push_back(predSet->getOperand(1)); in AnalyzeBranch()
241 Cond.push_back(predSet->getOperand(2)); in AnalyzeBranch()
242 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); in AnalyzeBranch()
264 const SmallVectorImpl<MachineOperand> &Cond, in InsertBranch() argument
270 if (Cond.empty()) { in InsertBranch()
277 PredSet->getOperand(2).setImm(Cond[1].getImm()); in InsertBranch()
[all …]
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | R600InstrInfo.cpp | 180 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
216 Cond.push_back(predSet->getOperand(1)); in AnalyzeBranch()
217 Cond.push_back(predSet->getOperand(2)); in AnalyzeBranch()
218 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); in AnalyzeBranch()
240 Cond.push_back(predSet->getOperand(1)); in AnalyzeBranch()
241 Cond.push_back(predSet->getOperand(2)); in AnalyzeBranch()
242 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); in AnalyzeBranch()
264 const SmallVectorImpl<MachineOperand> &Cond, in InsertBranch() argument
270 if (Cond.empty()) { in InsertBranch()
277 PredSet->getOperand(2).setImm(Cond[1].getImm()); in InsertBranch()
[all …]
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| /external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| D | ConstraintManager.h | 68 DefinedSVal Cond,
75 ProgramStatePair assumeDual(ProgramStateRef State, DefinedSVal Cond) { in assumeDual() argument
76 ProgramStateRef StTrue = assume(State, Cond, true); in assumeDual()
86 assert(assume(State, Cond, false) && "System is over constrained."); in assumeDual()
91 ProgramStateRef StFalse = assume(State, Cond, false); in assumeDual()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 172 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const { in AnalyzeBranch() argument
189 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
207 Cond.push_back(SecondLastInst->getOperand(0)); in AnalyzeBranch()
253 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const { in InsertBranch() argument
256 assert((Cond.size() == 1 || Cond.size() == 0) && in InsertBranch()
261 if (Cond.empty()) // Unconditional branch in InsertBranch()
264 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()) in InsertBranch()
270 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB); in InsertBranch()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 339 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
371 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
372 Cond.push_back(LastInst->getOperand(1)); in AnalyzeBranch()
379 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in AnalyzeBranch()
380 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
387 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); in AnalyzeBranch()
388 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
397 Cond.push_back(MachineOperand::CreateImm(1)); in AnalyzeBranch()
398 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in AnalyzeBranch()
408 Cond.push_back(MachineOperand::CreateImm(0)); in AnalyzeBranch()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 61 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
68 Cond.push_back(LastInst->getOperand(0)); in parseCondBranch()
75 Cond.push_back(MachineOperand::CreateImm(-1)); in parseCondBranch()
76 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in parseCondBranch()
77 Cond.push_back(LastInst->getOperand(0)); in parseCondBranch()
84 Cond.push_back(MachineOperand::CreateImm(-1)); in parseCondBranch()
85 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in parseCondBranch()
86 Cond.push_back(LastInst->getOperand(0)); in parseCondBranch()
87 Cond.push_back(LastInst->getOperand(1)); in parseCondBranch()
95 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
[all …]
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