| /external/clang/include/clang/AST/ |
| D | Attr.h | 53 bool Implicit : 1; variable
78 Inherited(false), IsPackExpansion(false), Implicit(false) {} in Range()
97 bool isImplicit() const { return Implicit; } in isImplicit()
98 void setImplicit(bool I) { Implicit = I; } in setImplicit()
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| D | LambdaCapture.h | 62 LambdaCapture(SourceLocation Loc, bool Implicit, LambdaCaptureKind Kind,
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| D | DeclBase.h | 250 unsigned Implicit : 1; variable
317 HasAttrs(false), Implicit(false), Used(false), Referenced(false), in Decl()
327 HasAttrs(false), Implicit(false), Used(false), Referenced(false), in Decl()
496 bool isImplicit() const { return Implicit; } in isImplicit()
497 void setImplicit(bool I = true) { Implicit = I; }
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 32 Implicit = 0x4, enumerator
40 ImplicitDefine = Implicit | Define,
41 ImplicitKill = Implicit | Kill
70 flags & RegState::Implicit,
392 return B ? RegState::Implicit : 0; in getImplRegState()
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| /external/llvm/test/YAMLParser/ |
| D | spec-07-12a.data | 3 # Implicit document. Root
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| D | spec-10-11.data | 6 ? explicit key3, # Implicit empty
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| /external/chromium_org/ui/accessibility/ |
| D | ax_enums.idl | 19 // Implicit: it would be cleaner if we just updated the AX node
28 aria_attribute_changed, // Implicit
31 checked_state_changed, // Implicit
36 invalid_status_changed, // Implicit
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| /external/llvm/lib/Target/R600/ |
| D | SILowerControlFlow.cpp | 414 .addReg(AMDGPU::M0, RegState::Implicit) in IndirectSrc()
415 .addReg(Vec, RegState::Implicit); in IndirectSrc()
436 .addReg(AMDGPU::M0, RegState::Implicit) in IndirectDst()
437 .addReg(Dst, RegState::Implicit); in IndirectDst()
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| D | R600InstrInfo.cpp | 73 RegState::Define | RegState::Implicit); in copyPhysReg()
1033 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
1041 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
1143 RegState::Implicit | RegState::Kill); in buildIndirectWrite()
1176 RegState::Implicit | RegState::Kill); in buildIndirectRead()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600ISelLowering.cpp | 173 .addReg(t0, RegState::Implicit) in EmitInstrWithCustomInserter()
174 .addReg(t1, RegState::Implicit); in EmitInstrWithCustomInserter()
195 .addReg(t0, RegState::Implicit) in EmitInstrWithCustomInserter()
196 .addReg(t1, RegState::Implicit); in EmitInstrWithCustomInserter()
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| D | R600InstrInfo.cpp | 63 .addReg(DestReg, RegState::Define | RegState::Implicit); in copyPhysReg()
463 MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | R600ISelLowering.cpp | 173 .addReg(t0, RegState::Implicit) in EmitInstrWithCustomInserter()
174 .addReg(t1, RegState::Implicit); in EmitInstrWithCustomInserter()
195 .addReg(t0, RegState::Implicit) in EmitInstrWithCustomInserter()
196 .addReg(t1, RegState::Implicit); in EmitInstrWithCustomInserter()
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| D | R600InstrInfo.cpp | 63 .addReg(DestReg, RegState::Define | RegState::Implicit); in copyPhysReg()
463 MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
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| /external/eigen/doc/ |
| D | TopicLinearAlgebraDecompositions.dox | 38 <td>Blocking, Implicit MT</td>
249 <dt><b>Implicit Multi Threading (MT)</b></dt>
250 …<dd>Means the algorithm can take advantage of multicore processors via OpenMP. "Implicit" means th…
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| /external/libexif/m4m/ |
| D | gp-packaging.m4 | 41 # FIXME: Implicit dependency
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| D | gp-check-popt.m4 | 56 dnl Implicit AC_SUBST
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| /external/llvm/lib/Target/X86/ |
| D | X86ScheduleSLM.td | 139 // Packed Compare Implicit Length Strings, Return Mask
159 // Packed Compare Implicit Length Strings, Return Index
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| D | X86SchedSandyBridge.td | 160 // Packed Compare Implicit Length Strings, Return Mask
180 // Packed Compare Implicit Length Strings, Return Index
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| D | X86SchedHaswell.td | 182 // Packed Compare Implicit Length Strings, Return Mask
202 // Packed Compare Implicit Length Strings, Return Index
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| D | X86Schedule.td | 98 // Packed Compare Implicit Length Strings, Return Mask
102 // Packed Compare Implicit Length Strings, Return Index
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| /external/clang/test/SemaObjCXX/ |
| D | instantiate-expr.mm | 55 // Implicit setter/getter
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 1231 MIB.addReg(SrcRegS, RegState::Implicit); in expandPostRAPseudo()
4115 MIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
4146 MIB.addReg(DstReg, RegState::Define | RegState::Implicit); in setExecutionDomain()
4148 MIB.addReg(ImplicitSReg, RegState::Implicit); in setExecutionDomain()
4181 MIB.addReg(DstReg, RegState::Implicit | RegState::Define); in setExecutionDomain()
4182 MIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
4184 MIB.addReg(ImplicitSReg, RegState::Implicit); in setExecutionDomain()
4219 NewMIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
4238 MIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
4242 MIB.addReg(DstReg, RegState::Define | RegState::Implicit); in setExecutionDomain()
[all …]
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| /external/clang/test/FixIt/ |
| D | format.m | 236 } Implicit;
248 …printf("%f", (Implicit)0); // expected-warning{{format specifies type 'double' but the argument ha…
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 111 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
537 SrcReg, RegState::Implicit); in expandExtractElementF64()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 1324 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
1348 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
1566 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define); in copyPhysReg()
1575 .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
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