| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 189 static const CostTblEntry<MVT::SimpleValueType> NEONFltDblTbl[] = { in getCastInstrCost()
191 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
192 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
193 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
198 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src); in getCastInstrCost()
213 static const TypeConversionCostTblEntry<MVT::SimpleValueType> in getCastInstrCost()
215 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
216 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
217 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
218 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 28 class MVT {
158 MVT() : SimpleTy((SimpleValueType)(INVALID_SIMPLE_VALUE_TYPE)) {} in MVT() function
159 MVT(SimpleValueType SVT) : SimpleTy(SVT) { } in MVT() function
161 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
162 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
163 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
164 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
165 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
166 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
170 return ((SimpleTy >= MVT::FIRST_FP_VALUETYPE && in isFloatingPoint()
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 115 case MVT::i1: return "i1"; in getEVTString()
116 case MVT::i8: return "i8"; in getEVTString()
117 case MVT::i16: return "i16"; in getEVTString()
118 case MVT::i32: return "i32"; in getEVTString()
119 case MVT::i64: return "i64"; in getEVTString()
120 case MVT::i128: return "i128"; in getEVTString()
121 case MVT::f16: return "f16"; in getEVTString()
122 case MVT::f32: return "f32"; in getEVTString()
123 case MVT::f64: return "f64"; in getEVTString()
124 case MVT::f80: return "f80"; in getEVTString()
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| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 185 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty); in getArithmeticInstrCost()
190 static const CostTblEntry<MVT::SimpleValueType> in getArithmeticInstrCost()
192 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
193 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
194 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
195 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
205 static const CostTblEntry<MVT::SimpleValueType> AVX2CostTable[] = { in getArithmeticInstrCost()
208 { ISD::SHL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
209 { ISD::SRL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
210 { ISD::SRA, MVT::v4i32, 1 }, in getArithmeticInstrCost()
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| D | X86ISelLowering.cpp | 241 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; in resetOperationActions()
303 addRegisterClass(MVT::i8, &X86::GR8RegClass); in resetOperationActions()
304 addRegisterClass(MVT::i16, &X86::GR16RegClass); in resetOperationActions()
305 addRegisterClass(MVT::i32, &X86::GR32RegClass); in resetOperationActions()
307 addRegisterClass(MVT::i64, &X86::GR64RegClass); in resetOperationActions()
309 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in resetOperationActions()
312 setTruncStoreAction(MVT::i64, MVT::i32, Expand); in resetOperationActions()
313 setTruncStoreAction(MVT::i64, MVT::i16, Expand); in resetOperationActions()
314 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); in resetOperationActions()
315 setTruncStoreAction(MVT::i32, MVT::i16, Expand); in resetOperationActions()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 306 static const TypeConversionCostTblEntry<MVT> ConversionTbl[] = { in getCastInstrCost()
308 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
309 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
310 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
311 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
312 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
313 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
316 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
317 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
318 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
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| D | AArch64ISelDAGToDAG.cpp | 250 Val = CurDAG->getTargetConstant(Immed, MVT::i32); in SelectArithImmed()
251 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32); in SelectArithImmed()
276 if (N.getValueType() == MVT::i32) in SelectNegArithImmed()
284 return SelectArithImmed(CurDAG->getConstant(Immed, MVT::i32), Val, Shift); in SelectNegArithImmed()
332 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32); in SelectShiftedRegister()
351 if (!IsLoadStore && SrcVT == MVT::i8) in getExtendTypeForNode()
353 else if (!IsLoadStore && SrcVT == MVT::i16) in getExtendTypeForNode()
355 else if (SrcVT == MVT::i32) in getExtendTypeForNode()
357 assert(SrcVT != MVT::i64 && "extend from 64-bits?"); in getExtendTypeForNode()
363 if (!IsLoadStore && SrcVT == MVT::i8) in getExtendTypeForNode()
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| D | AArch64FastISel.cpp | 113 bool isTypeLegal(Type *Ty, MVT &VT);
114 bool isLoadStoreTypeLegal(Type *Ty, MVT &VT);
116 bool SimplifyAddress(Address &Addr, MVT VT, int64_t ScaleFactor,
125 bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
127 bool EmitStore(MVT VT, unsigned SrcReg, Address Addr,
129 unsigned EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
130 unsigned Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
132 unsigned AArch64MaterializeFP(const ConstantFP *CFP, MVT VT);
140 SmallVectorImpl<MVT> &ArgVTs,
144 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
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| D | AArch64ISelLowering.cpp | 89 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass); in AArch64TargetLowering()
90 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass); in AArch64TargetLowering()
93 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
94 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass); in AArch64TargetLowering()
95 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); in AArch64TargetLowering()
96 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); in AArch64TargetLowering()
100 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass); in AArch64TargetLowering()
101 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
103 addDRTypeForNEON(MVT::v2f32); in AArch64TargetLowering()
104 addDRTypeForNEON(MVT::v8i8); in AArch64TargetLowering()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 421 if (OpVT == MVT::f32) { in getFPEXT()
422 if (RetVT == MVT::f64) in getFPEXT()
424 if (RetVT == MVT::f128) in getFPEXT()
426 } else if (OpVT == MVT::f64) { in getFPEXT()
427 if (RetVT == MVT::f128) in getFPEXT()
437 if (RetVT == MVT::f32) { in getFPROUND()
438 if (OpVT == MVT::f64) in getFPROUND()
440 if (OpVT == MVT::f80) in getFPROUND()
442 if (OpVT == MVT::f128) in getFPROUND()
444 if (OpVT == MVT::ppcf128) in getFPROUND()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 65 CC_Hexagon(unsigned ValNo, MVT ValVT,
66 MVT LocVT, CCValAssign::LocInfo LocInfo,
70 CC_Hexagon32(unsigned ValNo, MVT ValVT,
71 MVT LocVT, CCValAssign::LocInfo LocInfo,
75 CC_Hexagon64(unsigned ValNo, MVT ValVT,
76 MVT LocVT, CCValAssign::LocInfo LocInfo,
80 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
81 MVT LocVT, CCValAssign::LocInfo LocInfo,
85 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
86 MVT LocVT, CCValAssign::LocInfo LocInfo,
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| D | HexagonISelDAGToDAG.cpp | 123 return CurDAG->getTargetConstant(bitPos, MVT::i32); in XformMskToBitPosU5Imm()
151 return CurDAG->getTargetConstant( - Imm, MVT::i32); in XformM5ToU5Imm()
159 return CurDAG->getTargetConstant(Imm - 1, MVT::i8); in XformU7ToU7M1Imm()
164 return CurDAG->getTargetConstant(Imm - 1, MVT::i32); in XformSToSM1Imm()
170 return CurDAG->getTargetConstant(Imm - 1, MVT::i32); in XformUToUM1Imm()
366 if (MemType == MVT::i64 && isShiftedInt<11,3>(Offset)) { in OffsetFitsS11()
369 if (MemType == MVT::i32 && isShiftedInt<11,2>(Offset)) { in OffsetFitsS11()
372 if (MemType == MVT::i16 && isShiftedInt<11,1>(Offset)) { in OffsetFitsS11()
375 if (MemType == MVT::i8 && isInt<11>(Offset)) { in OffsetFitsS11()
398 MVT PointerTy = getTargetLowering()->getPointerTy(); in SelectBaseOffsetLoad()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelDAGToDAG.cpp | 329 return CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N), MVT::i64, in SelectTexSurfHandle()
418 MVT SimpleVT = LoadedVT.getSimpleVT(); in SelectLoad()
436 MVT ScalarVT = SimpleVT.getScalarType(); in SelectLoad()
453 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy; in SelectLoad()
457 case MVT::i8: in SelectLoad()
460 case MVT::i16: in SelectLoad()
463 case MVT::i32: in SelectLoad()
466 case MVT::i64: in SelectLoad()
469 case MVT::f32: in SelectLoad()
472 case MVT::f64: in SelectLoad()
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| D | NVPTXISelLowering.cpp | 51 static bool IsPTXVectorType(MVT VT) { in IsPTXVectorType()
55 case MVT::v2i1: in IsPTXVectorType()
56 case MVT::v4i1: in IsPTXVectorType()
57 case MVT::v2i8: in IsPTXVectorType()
58 case MVT::v4i8: in IsPTXVectorType()
59 case MVT::v2i16: in IsPTXVectorType()
60 case MVT::v4i16: in IsPTXVectorType()
61 case MVT::v2i32: in IsPTXVectorType()
62 case MVT::v4i32: in IsPTXVectorType()
63 case MVT::v2i64: in IsPTXVectorType()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 38 MVT::SimpleValueType llvm::getValueType(Record *Rec) { in getValueType()
39 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); in getValueType()
42 std::string llvm::getName(MVT::SimpleValueType T) { in getName()
44 case MVT::Other: return "UNKNOWN"; in getName()
45 case MVT::iPTR: return "TLI.getPointerTy()"; in getName()
46 case MVT::iPTRAny: return "TLI.getPointerTy()"; in getName()
51 std::string llvm::getEnumName(MVT::SimpleValueType T) { in getEnumName()
53 case MVT::Other: return "MVT::Other"; in getEnumName()
54 case MVT::i1: return "MVT::i1"; in getEnumName()
55 case MVT::i8: return "MVT::i8"; in getEnumName()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 51 (int)MVT::i8, in InitAMDILLowering()
52 (int)MVT::i16, in InitAMDILLowering()
53 (int)MVT::i32, in InitAMDILLowering()
54 (int)MVT::f32, in InitAMDILLowering()
55 (int)MVT::f64, in InitAMDILLowering()
56 (int)MVT::i64, in InitAMDILLowering()
57 (int)MVT::v2i8, in InitAMDILLowering()
58 (int)MVT::v4i8, in InitAMDILLowering()
59 (int)MVT::v2i16, in InitAMDILLowering()
60 (int)MVT::v4i16, in InitAMDILLowering()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 51 (int)MVT::i8, in InitAMDILLowering()
52 (int)MVT::i16, in InitAMDILLowering()
53 (int)MVT::i32, in InitAMDILLowering()
54 (int)MVT::f32, in InitAMDILLowering()
55 (int)MVT::f64, in InitAMDILLowering()
56 (int)MVT::i64, in InitAMDILLowering()
57 (int)MVT::v2i8, in InitAMDILLowering()
58 (int)MVT::v4i8, in InitAMDILLowering()
59 (int)MVT::v2i16, in InitAMDILLowering()
60 (int)MVT::v4i16, in InitAMDILLowering()
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 33 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); in SITargetLowering()
34 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); in SITargetLowering()
36 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass); in SITargetLowering()
37 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass); in SITargetLowering()
39 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass); in SITargetLowering()
40 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass); in SITargetLowering()
42 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass); in SITargetLowering()
43 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); in SITargetLowering()
44 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass); in SITargetLowering()
46 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass); in SITargetLowering()
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| D | AMDGPUISelLowering.cpp | 75 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT, in allocateStack()
94 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); in getEquivalentMemType()
103 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); in getEquivalentLoadRegType()
111 setOperationAction(ISD::Constant, MVT::i32, Legal); in AMDGPUTargetLowering()
112 setOperationAction(ISD::Constant, MVT::i64, Legal); in AMDGPUTargetLowering()
113 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in AMDGPUTargetLowering()
114 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); in AMDGPUTargetLowering()
116 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in AMDGPUTargetLowering()
117 setOperationAction(ISD::BRIND, MVT::Other, Expand); in AMDGPUTargetLowering()
120 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in AMDGPUTargetLowering()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 110 unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
141 bool isTypeLegal(Type *Ty, MVT &VT);
142 bool isLoadTypeLegal(Type *Ty, MVT &VT);
145 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
148 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
150 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
152 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
154 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
155 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
156 unsigned PPCMaterializeInt(const Constant *C, MVT VT);
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| D | PPCISelDAGToDAG.cpp | 83 return CurDAG->getTargetConstant(Imm, MVT::i32); in getI32Imm()
89 return CurDAG->getTargetConstant(Imm, MVT::i64); in getI64Imm()
277 if (PPCLowering->getPointerTy() == MVT::i32) { in getGlobalBaseReg()
300 if (N->getValueType(0) == MVT::i32) in isIntS16Immediate()
314 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { in isInt32Immediate()
324 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { in isInt64Immediate()
375 if (N->getValueType(0) != MVT::i32) in isRotateAndMask()
484 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); in SelectBitfieldInsert()
497 if (LHS.getValueType() == MVT::i32) { in SelectCC()
503 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, in SelectCC()
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| D | PPCISelLowering.cpp | 78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in PPCTargetLowering()
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); in PPCTargetLowering()
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in PPCTargetLowering()
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 39 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_SRet()
40 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_SRet()
52 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_f64()
53 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_f64()
81 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, in CC_Sparc64_Full()
82 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc64_Full()
84 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in CC_Sparc64_Full()
89 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
90 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
94 if (LocVT == MVT::i64 && Offset < 6*8) in CC_Sparc64_Full()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 76 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); in XCoreTargetLowering()
93 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in XCoreTargetLowering()
94 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in XCoreTargetLowering()
95 setOperationAction(ISD::ADDC, MVT::i32, Expand); in XCoreTargetLowering()
96 setOperationAction(ISD::ADDE, MVT::i32, Expand); in XCoreTargetLowering()
97 setOperationAction(ISD::SUBC, MVT::i32, Expand); in XCoreTargetLowering()
98 setOperationAction(ISD::SUBE, MVT::i32, Expand); in XCoreTargetLowering()
101 setOperationAction(ISD::ADD, MVT::i64, Custom); in XCoreTargetLowering()
102 setOperationAction(ISD::SUB, MVT::i64, Custom); in XCoreTargetLowering()
103 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); in XCoreTargetLowering()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 72 bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
74 bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
80 bool isTypeLegal(Type *Ty, MVT &VT);
81 bool isLoadTypeLegal(Type *Ty, MVT &VT);
83 unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
84 unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
85 unsigned MaterializeInt(const Constant *C, MVT VT);
119 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
122 if (evt == MVT::Other || !evt.isSimple()) in isTypeLegal()
131 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal()
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