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Searched refs:Regs (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonCallingConvLower.h109 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { in getFirstUnallocated() argument
111 if (!isAllocated(Regs[i])) in getFirstUnallocated()
136 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { in AllocateReg() argument
137 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); in AllocateReg()
142 unsigned Reg = Regs[FirstUnalloc]; in AllocateReg()
148 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, in AllocateReg() argument
150 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); in AllocateReg()
155 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; in AllocateReg()
/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp57 const std::vector<CodeGenRegister*> &Regs, bool isCtor);
59 const std::vector<CodeGenRegister*> &Regs,
171 const CodeGenRegister::Set &Regs = RC.getMembers(); in EmitRegUnitPressure() local
172 if (Regs.empty()) in EmitRegUnitPressure()
177 OS << " {" << (*Regs.begin())->getWeight(RegBank) in EmitRegUnitPressure()
315 const std::vector<CodeGenRegister*> &Regs, in EmitRegMappingTables() argument
323 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in EmitRegMappingTables()
324 Record *Reg = Regs[i]->TheDef; in EmitRegMappingTables()
342 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace"); in EmitRegMappingTables()
390 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in EmitRegMappingTables()
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DCodeGenRegisters.cpp159 RegUnitIterator(const CodeGenRegister::Set &Regs): in RegUnitIterator() argument
160 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() { in RegUnitIterator()
941 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local
942 std::sort(Regs.begin(), Regs.end(), LessRecordRegister()); in CodeGenRegBank()
943 Registers.reserve(Regs.size()); in CodeGenRegBank()
945 for (unsigned i = 0, e = Regs.size(); i != e; ++i) in CodeGenRegBank()
946 getReg(Regs[i]); in CodeGenRegBank()
1232 CodeGenRegister::Set Regs; member
1263 const CodeGenRegister::Set &Regs = RegClass->getMembers(); in computeUberSets() local
1264 if (Regs.empty()) in computeUberSets()
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DCodeGenTarget.cpp226 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); in getRegisterByName() local
227 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name); in getRegisterByName()
228 if (I == Regs.end()) in getRegisterByName()
DCodeGenRegisters.h675 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
DAsmMatcherEmitter.cpp2187 const std::vector<CodeGenRegister*> &Regs = in emitMatchRegisterName() local
2189 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in emitMatchRegisterName()
2190 const CodeGenRegister *Reg = Regs[i]; in emitMatchRegisterName()
/external/llvm/include/llvm/CodeGen/
DCallingConvLower.h300 unsigned getFirstUnallocated(const MCPhysReg *Regs, unsigned NumRegs) const { in getFirstUnallocated() argument
302 if (!isAllocated(Regs[i])) in getFirstUnallocated()
327 unsigned AllocateReg(const MCPhysReg *Regs, unsigned NumRegs) { in AllocateReg() argument
328 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); in AllocateReg()
333 unsigned Reg = Regs[FirstUnalloc]; in AllocateReg()
341 unsigned AllocateRegBlock(const uint16_t *Regs, unsigned NumRegs, unsigned RegsRequired) { in AllocateRegBlock() argument
346 if (isAllocated(Regs[StartIdx + BlockIdx])) { in AllocateRegBlock()
354 MarkAllocated(Regs[StartIdx + BlockIdx]); in AllocateRegBlock()
356 return Regs[StartIdx]; in AllocateRegBlock()
364 unsigned AllocateReg(const MCPhysReg *Regs, const MCPhysReg *ShadowRegs, in AllocateReg() argument
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DRegisterScavenging.h180 void setUsed(BitVector &Regs) { in setUsed() argument
181 RegsAvailable.reset(Regs); in setUsed()
183 void setUnused(BitVector &Regs) { in setUnused() argument
184 RegsAvailable |= Regs; in setUnused()
DRegisterPressure.h305 void addLiveRegs(ArrayRef<unsigned> Regs);
430 void increaseRegPressure(ArrayRef<unsigned> Regs);
431 void decreaseRegPressure(ArrayRef<unsigned> Regs);
/external/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp52 const unsigned *Regs) { in decodeRegisterClass() argument
54 RegNo = Regs[RegNo]; in decodeRegisterClass()
190 const unsigned *Regs) { in decodeBDAddr12Operand() argument
194 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
200 const unsigned *Regs) { in decodeBDAddr20Operand() argument
204 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
210 const unsigned *Regs) { in decodeBDXAddr12Operand() argument
215 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
217 Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
222 const unsigned *Regs) { in decodeBDXAddr20Operand() argument
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/external/llvm/lib/Target/SystemZ/AsmParser/
DSystemZAsmParser.cpp313 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
317 RegisterGroup Group, const unsigned *Regs,
322 const unsigned *Regs, RegisterKind RegKind);
325 const unsigned *Regs, RegisterKind RegKind,
461 const unsigned *Regs, bool IsAddress) { in parseRegister() argument
466 if (Regs && Regs[Reg.Num] == 0) in parseRegister()
470 if (Regs) in parseRegister()
471 Reg.Num = Regs[Reg.Num]; in parseRegister()
478 const unsigned *Regs, RegisterKind Kind) { in parseRegister() argument
484 if (parseRegister(Reg, Group, Regs, IsAddress)) in parseRegister()
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/external/llvm/lib/CodeGen/AsmPrinter/
DDbgValueHistoryCalculator.cpp117 std::set<unsigned> &Regs) { in collectClobberedRegisters() argument
122 Regs.insert(*AI); in collectClobberedRegisters()
151 std::set<unsigned> &Regs) { in collectChangingRegs() argument
158 collectClobberedRegisters(MI, TRI, Regs); in collectChangingRegs()
/external/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp71 std::vector<unsigned> &Regs, in GetGroupRegs() argument
76 Regs.push_back(Reg); in GetGroupRegs()
548 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
549 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); in FindSuitableFreeRegisters()
550 assert(Regs.size() > 0 && "Empty register group!"); in FindSuitableFreeRegisters()
551 if (Regs.size() == 0) in FindSuitableFreeRegisters()
561 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
562 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
581 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
582 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
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DExecutionDepsFix.cpp644 SmallVector<LiveReg, 4> Regs; in visitSoftInstr() local
655 for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end(); in visitSoftInstr()
659 Regs.insert(i, LR); in visitSoftInstr()
663 Regs.push_back(LR); in visitSoftInstr()
669 while (!Regs.empty()) { in visitSoftInstr()
671 dv = Regs.pop_back_val().Value; in visitSoftInstr()
678 DomainValue *Latest = Regs.pop_back_val().Value; in visitSoftInstr()
DAggressiveAntiDepBreaker.h97 std::vector<unsigned> &Regs,
DRegisterPressure.cpp423 void RegPressureTracker::addLiveRegs(ArrayRef<unsigned> Regs) { in addLiveRegs() argument
424 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in addLiveRegs()
425 if (LiveRegs.insert(Regs[i])) in addLiveRegs()
426 increaseRegPressure(Regs[i]); in addLiveRegs()
/external/llvm/lib/Target/ARM/
DARMFrameLowering.cpp811 SmallVector<std::pair<unsigned,bool>, 4> Regs; in emitPushInst() local
843 Regs.push_back(std::make_pair(Reg, isKill)); in emitPushInst()
846 if (Regs.empty()) in emitPushInst()
848 if (Regs.size() > 1 || StrOpc== 0) { in emitPushInst()
852 for (unsigned i = 0, e = Regs.size(); i < e; ++i) in emitPushInst()
853 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); in emitPushInst()
854 } else if (Regs.size() == 1) { in emitPushInst()
857 .addReg(Regs[0].first, getKillRegState(Regs[0].second)) in emitPushInst()
862 Regs.clear(); in emitPushInst()
888 SmallVector<unsigned, 4> Regs; in emitPopInst() local
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DARMLoadStoreOptimizer.cpp108 ArrayRef<std::pair<unsigned, bool> > Regs,
418 ArrayRef<std::pair<unsigned, bool> > Regs, in MergeOps()
421 unsigned NumRegs = Regs.size(); in MergeOps()
452 NewBase = Regs[NumRegs-1].first; in MergeOps()
510 if (Base == Regs[I].first) { in MergeOps()
542 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) in MergeOps()
543 | getKillRegState(Regs[i].second)); in MergeOps()
638 SmallVector<std::pair<unsigned, bool>, 8> Regs; in MergeOpsUpdate() local
646 Regs.push_back(std::make_pair(Reg, isKill)); in MergeOpsUpdate()
668 Pred, PredReg, Scratch, dl, Regs, ImpDefs)) in MergeOpsUpdate()
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DThumb2SizeReduction.cpp214 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) in HasImplicitCPSRDef() local
215 if (*Regs == ARM::CPSR) in HasImplicitCPSRDef()
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp831 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple() argument
837 return createTuple(Regs, RegClassIDs, SubRegs); in createDTuple()
840 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() argument
846 return createTuple(Regs, RegClassIDs, SubRegs); in createQTuple()
849 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple() argument
854 if (Regs.size() == 1) in createTuple()
855 return Regs[0]; in createTuple()
857 assert(Regs.size() >= 2 && Regs.size() <= 4); in createTuple()
859 SDLoc DL(Regs[0].getNode()); in createTuple()
865 CurDAG->getTargetConstant(RegClassIDs[Regs.size() - 2], MVT::i32)); in createTuple()
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/external/llvm/lib/Transforms/Scalar/
DLoopStrengthReduce.cpp895 SmallPtrSet<const SCEV *, 16> &Regs,
908 SmallPtrSet<const SCEV *, 16> &Regs,
912 SmallPtrSet<const SCEV *, 16> &Regs,
922 SmallPtrSet<const SCEV *, 16> &Regs, in RateRegister() argument
944 if (!Regs.count(AR->getOperand(1))) { in RateRegister()
945 RateRegister(AR->getOperand(1), Regs, L, SE, DT); in RateRegister()
970 SmallPtrSet<const SCEV *, 16> &Regs, in RatePrimaryRegister() argument
978 if (Regs.insert(Reg)) { in RatePrimaryRegister()
979 RateRegister(Reg, Regs, L, SE, DT); in RatePrimaryRegister()
987 SmallPtrSet<const SCEV *, 16> &Regs, in RateFormula() argument
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/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp605 SmallVector<unsigned, 4> Regs; member
611 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} in RegsForValue()
622 Regs.push_back(Reg + i); in RegsForValue()
632 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); in append()
689 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); in getCopyFromRegs()
691 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); in getCopyFromRegs()
700 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || in getCopyFromRegs()
705 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); in getCopyFromRegs()
769 unsigned NumRegs = Regs.size(); in getCopyToRegs()
788 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); in getCopyToRegs()
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/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp173 const unsigned (&Regs)[N]) { in decodeRegisterClass()
175 Inst.addOperand(MCOperand::CreateReg(Regs[RegNo])); in decodeRegisterClass()
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp435 SmallVector<SDValue, 4> Regs; in LowerFormalArguments() local
436 Regs.push_back(Val); in LowerFormalArguments()
440 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT)); in LowerFormalArguments()
446 Regs.push_back(DAG.getUNDEF(VT)); in LowerFormalArguments()
448 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs)); in LowerFormalArguments()
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td86 class Uses<list<Register> Regs> {
87 list<Register> Uses = Regs;
90 class Defs<list<Register> Regs> {
91 list<Register> Defs = Regs;

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