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Searched refs:SimpleTy (Results 1 – 25 of 47) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DMachineValueType.h179 SimpleValueType SimpleTy; variable
181 LLVM_CONSTEXPR MVT() : SimpleTy(INVALID_SIMPLE_VALUE_TYPE) {} in MVT()
182 LLVM_CONSTEXPR MVT(SimpleValueType SVT) : SimpleTy(SVT) { } in MVT()
184 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
185 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
186 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
187 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
188 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
189 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
193 return (SimpleTy >= MVT::FIRST_VALUETYPE && in isValid()
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DValueTypes.h45 if (V.SimpleTy != VT.V.SimpleTy)
47 if (V.SimpleTy < 0)
63 if (M.SimpleTy >= 0) in getIntegerVT()
72 if (M.SimpleTy >= 0) in getVectorVT()
87 assert(VecTy.SimpleTy >= 0 && in changeVectorElementTypeToInteger()
108 return V.SimpleTy >= 0; in isSimple()
343 return V.SimpleTy; in getRawBits()
352 if (L.V.SimpleTy == R.V.SimpleTy) in operator()
355 return L.V.SimpleTy < R.V.SimpleTy; in operator()
/external/llvm/include/llvm/Target/
DTargetLowering.h381 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in getRegClassFor()
394 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; in getRepRegClassFor()
401 return RepRegClassCostForVT[VT.SimpleTy]; in getRepRegClassCostFor()
409 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); in isTypeLegal()
410 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr; in isTypeLegal()
425 return ValueTypeActions[VT.SimpleTy]; in getTypeAction()
429 ValueTypeActions[VT.SimpleTy] = Action; in setTypeAction()
553 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op]; in getOperationAction()
593 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; in getLoadExtAction()
594 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getLoadExtAction()
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/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.h90 if (LocVT.SimpleTy == MVT::i64) in CC_AArch64_Custom_Block()
92 else if (LocVT.SimpleTy == MVT::f16) in CC_AArch64_Custom_Block()
94 else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector()) in CC_AArch64_Custom_Block()
96 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
98 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector()) in CC_AArch64_Custom_Block()
DAArch64FastISel.cpp287 switch (VT.SimpleTy) { in getImplicitScaleFactor()
1094 switch (RetVT.SimpleTy) { in emitAddSub()
1113 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32); in emitAddSub()
1413 switch (VT.SimpleTy) { in emitCmp()
1603 MVT VT = std::max(MVT::i32, RetVT.SimpleTy); in emitLogicalOp()
1625 switch (RetVT.SimpleTy) { in emitLogicalOp_ri()
1676 switch (RetVT.SimpleTy) { in emitLogicalOp_rs()
1783 switch (VT.SimpleTy) { in emitLoad()
2034 switch (VT.SimpleTy) { in emitStore()
2564 switch (VT.SimpleTy) { in selectSelect()
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/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp724 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy; in SelectLoad()
969 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
993 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1022 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1046 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1076 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1100 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1123 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1147 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1178 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
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DNVPTXTargetTransformInfo.cpp113 if (LT.second.SimpleTy == MVT::i64) in getArithmeticInstrCost()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyAsmPrinter.cpp153 Param.addOperand(MCOperand::createImm(VT.SimpleTy)); in EmitFunctionBodyStart()
165 Result.addOperand(MCOperand::createImm(ResultVTs.front().SimpleTy)); in EmitFunctionBodyStart()
184 Local.addOperand(MCOperand::createImm(getRegType(VReg).SimpleTy)); in EmitFunctionBodyStart()
191 Local.addOperand(MCOperand::createImm(getRegType(PReg).SimpleTy)); in EmitFunctionBodyStart()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp353 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitLoad()
443 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
534 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
1163 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpOpcode()
1180 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpImmediateOpcode()
1343 if (SrcVT.SimpleTy == MVT::i1) { in X86SelectZExt()
1356 switch (SrcVT.SimpleTy) { in X86SelectZExt()
1473 switch (SourceVT.SimpleTy) { in X86SelectBranch()
1663 switch (VT.SimpleTy) { in X86SelectDivRem()
1707 if (VT.SimpleTy == MVT::i16) { in X86SelectDivRem()
[all …]
DX86ISelDAGToDAG.cpp1946 switch (NVT.SimpleTy) { in selectAtomicLoadArith()
2364 switch (NVT.SimpleTy) { in Select()
2425 switch (NVT.SimpleTy) { in Select()
2454 switch (NVT.SimpleTy) { in Select()
2464 switch (NVT.SimpleTy) { in Select()
2605 switch (NVT.SimpleTy) { in Select()
2613 switch (NVT.SimpleTy) { in Select()
2624 switch (NVT.SimpleTy) { in Select()
2679 switch (NVT.SimpleTy) { in Select()
2813 switch (N0.getSimpleValueType().SimpleTy) { in Select()
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/external/mesa3d/src/gallium/drivers/radeon/
DSIRegisterInfo.cpp55 switch(VT.SimpleTy) { in getCFGStructurizerRegClass()
DR600RegisterInfo.cpp110 switch(VT.SimpleTy) { in getCFGStructurizerRegClass()
DAMDILISelLowering.cpp252 if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32 in isFPImmLegal()
253 || VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) { in isFPImmLegal()
263 if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32 in ShouldShrinkFPConstant()
264 || VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) { in ShouldShrinkFPConstant()
/external/llvm/lib/Target/AMDGPU/
DR600RegisterInfo.cpp69 switch(VT.SimpleTy) { in getCFGStructurizerRegClass()
/external/llvm/lib/Target/WebAssembly/InstPrinter/
DWebAssemblyInstPrinter.cpp117 switch (Ty.SimpleTy) { in TypeToString()
/external/llvm/lib/Target/MSP430/
DMSP430ISelDAGToDAG.cpp307 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad()
335 switch (VT.SimpleTy) { in SelectIndexedLoad()
/external/llvm/lib/IR/
DValueTypes.cpp116 switch (V.SimpleTy) { in getEVTString()
200 switch (V.SimpleTy) { in getTypeForEVT()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp863 switch (VT.SimpleTy) { in ARMSimplifyAddress()
918 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64) in AddLoadStoreOperands()
964 switch (VT.SimpleTy) { in ARMEmitLoad()
1085 switch (VT.SimpleTy) { in ARMEmitStore()
1400 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1823 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in SelectBinaryFPOp()
1910 switch (ArgVT.SimpleTy) { in ProcessCallArgs()
3028 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
DARMCallingConv.h207 switch (LocVT.SimpleTy) { in CC_ARM_AAPCS_Custom_Aggregate()
DARMISelDAGToDAG.cpp1556 switch (LoadedVT.getSimpleVT().SimpleTy) { in SelectT2IndexedLoad()
1822 switch (VT.getSimpleVT().SimpleTy) { in SelectVLD()
1959 switch (VT.getSimpleVT().SimpleTy) { in SelectVST()
2122 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDSTLane()
2235 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDDup()
2773 switch (VT.getSimpleVT().SimpleTy) { in Select()
2793 switch (VT.getSimpleVT().SimpleTy) { in Select()
2813 switch (VT.getSimpleVT().SimpleTy) { in Select()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp659 switch (VT.SimpleTy) { \ in getATOMIC()
905 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); in getTypeConversion()
906 MVT NVT = TransformToType[SVT.SimpleTy]; in getTypeConversion()
1156 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in findRepresentativeClass()
1369 return getPointerTy(DL).SimpleTy; in getSetCCResultType()
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp710 switch (VT.SimpleTy) { in emitLoad()
771 switch (VT.SimpleTy) { in emitStore()
1565 switch (SrcVT.SimpleTy) { in emitIntSExt32r1()
1583 switch (SrcVT.SimpleTy) { in emitIntSExt32r2()
1609 switch (SrcVT.SimpleTy) { in emitIntZExt()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp212 switch (RegVT.getSimpleVT().SimpleTy) { in LowerFormalArguments()
215 << RegVT.getSimpleVT().SimpleTy << '\n'; in LowerFormalArguments()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp268 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); in ExpandConstantFP()
2312 switch (Node->getSimpleValueType(0).SimpleTy) { in ExpandFPLibCall()
2330 switch (Node->getSimpleValueType(0).SimpleTy) { in ExpandIntLibCall()
2349 switch (Node->getSimpleValueType(0).SimpleTy) { in ExpandDivRemLibCall()
2407 switch (Node->getSimpleValueType(0).SimpleTy) { in isSinCosLibcallAvailable()
2455 switch (Node->getSimpleValueType(0).SimpleTy) { in ExpandSinCosLibCall()
2689 switch (Op0.getSimpleValueType().SimpleTy) { in ExpandLegalINT_TO_FP()
2741 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); in PromoteLegalINT_TO_FP()
2783 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); in PromoteLegalFP_TO_INT()
2841 switch (VT.getSimpleVT().SimpleTy) { in ExpandBSWAP()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp472 switch (VT.SimpleTy) { in PPCEmitLoad()
615 switch (VT.SimpleTy) { in PPCEmitStore()
832 switch (SrcVT.SimpleTy) { in PPCEmitCmp()

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