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Searched refs:Subtarget (Results 1 – 25 of 155) sorted by relevance

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/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.cpp86 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>(); in getCalleeSavedRegs() local
89 if (Subtarget.hasMips64()) in getCalleeSavedRegs()
90 return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList in getCalleeSavedRegs()
93 return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList in getCalleeSavedRegs()
97 if (Subtarget.isSingleFloat()) in getCalleeSavedRegs()
100 if (Subtarget.isABI_N64()) in getCalleeSavedRegs()
103 if (Subtarget.isABI_N32()) in getCalleeSavedRegs()
106 if (Subtarget.isFP64bit()) in getCalleeSavedRegs()
109 if (Subtarget.isFPXX()) in getCalleeSavedRegs()
118 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>(); in getCallPreservedMask() local
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DMipsSEInstrInfo.cpp84 bool isMicroMips = Subtarget.inMicroMipsMode(); in copyPhysReg()
312 if (Subtarget.getABI().ArePtrs64bit()) { in loadRegFromStack()
330 bool isMicroMips = Subtarget.inMicroMipsMode(); in expandPostRAPseudo()
430 MipsABIInfo ABI = Subtarget.getABI(); in adjustStackPtr()
453 const MipsSubtarget &STI = Subtarget; in loadImmediate()
502 if (Subtarget.isGP64bit()) in expandRetRA()
600 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); in expandExtractElementF64()
604 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); in expandExtractElementF64()
606 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) { in expandExtractElementF64()
651 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); in expandBuildPairF64()
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DMipsISelLowering.cpp227 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { in MipsTargetLowering()
234 if (Subtarget.hasMips32r6()) in MipsTargetLowering()
289 if (Subtarget.isGP64bit()) { in MipsTargetLowering()
304 if (!Subtarget.isGP64bit()) { in MipsTargetLowering()
311 if (Subtarget.isGP64bit()) in MipsTargetLowering()
335 if (Subtarget.hasCnMips()) { in MipsTargetLowering()
353 if (!Subtarget.hasMips32r2()) in MipsTargetLowering()
356 if (!Subtarget.hasMips64r2()) in MipsTargetLowering()
394 if (!Subtarget.isGP64bit()) { in MipsTargetLowering()
401 if (!Subtarget.hasMips32r2()) { in MipsTargetLowering()
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DMipsSEISelLowering.cpp44 if (Subtarget.isGP64bit()) in MipsSETargetLowering()
47 if (Subtarget.hasDSP() || Subtarget.hasMSA()) { in MipsSETargetLowering()
59 if (Subtarget.hasDSP()) { in MipsSETargetLowering()
83 if (Subtarget.hasDSPR2()) in MipsSETargetLowering()
86 if (Subtarget.hasMSA()) { in MipsSETargetLowering()
102 if (!Subtarget.useSoftFloat()) { in MipsSETargetLowering()
106 if (!Subtarget.isSingleFloat()) { in MipsSETargetLowering()
107 if (Subtarget.isFP64bit()) in MipsSETargetLowering()
119 if (Subtarget.hasCnMips()) in MipsSETargetLowering()
121 else if (Subtarget.isGP64bit()) in MipsSETargetLowering()
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DMips16ISelDAGToDAG.cpp40 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget()); in runOnMachineFunction()
41 if (!Subtarget->inMips16Mode()) in runOnMachineFunction()
75 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); in initGlobalBaseReg()
105 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); in initMips16SPAliasReg()
137 AliasReg = Subtarget->getFrameLowering()->hasFP(*MF) in getMips16SPRefReg()
149 AliasReg = Subtarget->getFrameLowering()->hasFP(*MF) in getMips16SPRefReg()
232 if (LS->getMemoryVT() == MVT::f32 && Subtarget->hasMips4_32r2()) in selectAddr16()
234 if (LS->getMemoryVT() == MVT::f64 && Subtarget->hasMips4_32r2()) in selectAddr16()
DMipsAsmPrinter.cpp61 Subtarget = &MF.getSubtarget<MipsSubtarget>(); in runOnMachineFunction()
68 if (Subtarget->inMips16Mode()) in runOnMachineFunction()
82 if (Subtarget->isTargetNaCl()) in runOnMachineFunction()
103 if (Subtarget->hasMips64r6()) { in emitPseudoIndirectBranch()
107 } else if (Subtarget->hasMips32r6()) { in emitPseudoIndirectBranch()
111 } else if (Subtarget->inMicroMipsMode()) in emitPseudoIndirectBranch()
122 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch()
200 if (I->isPseudo() && !Subtarget->inMips16Mode() in EmitInstruction()
326 if (Subtarget->isTargetNaCl()) in EmitFunctionEntryLabel()
329 if (Subtarget->inMicroMipsMode()) in EmitFunctionEntryLabel()
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/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp103 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); in getCalleeSavedRegs() local
105 if (Subtarget.hasVSX()) in getCalleeSavedRegs()
107 if (Subtarget.hasAltivec()) in getCalleeSavedRegs()
112 if (Subtarget.isDarwinABI()) in getCalleeSavedRegs()
114 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList in getCalleeSavedRegs()
116 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList in getCalleeSavedRegs()
123 ? (Subtarget.hasAltivec() in getCalleeSavedRegs()
127 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList in getCalleeSavedRegs()
134 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); in getCallPreservedMask() local
136 if (Subtarget.hasVSX()) in getCallPreservedMask()
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DPPCFrameLowering.cpp87 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), in PPCFrameLowering()
88 TOCSaveOffset(computeTOCSaveOffset(Subtarget)), in PPCFrameLowering()
89 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), in PPCFrameLowering()
90 LinkageSize(computeLinkageSize(Subtarget)), in PPCFrameLowering()
96 if (Subtarget.isDarwinABI()) { in getCalleeSavedSpillSlots()
98 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots()
108 if (!Subtarget.isSVR4ABI()) { in getCalleeSavedSpillSlots()
238 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots()
439 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); in determineFrameLayout()
449 (Subtarget.isPPC64() || // 32-bit SVR4, no stack- in determineFrameLayout()
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DPPCISelLowering.cpp59 : TargetLowering(TM), Subtarget(STI) { in PPCTargetLowering()
66 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering()
71 if (!Subtarget.useSoftFloat()) { in PPCTargetLowering()
100 if (Subtarget.useCRBits()) { in PPCTargetLowering()
103 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
177 if (!Subtarget.hasFSQRT() && in PPCTargetLowering()
178 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() && in PPCTargetLowering()
179 Subtarget.hasFRE())) in PPCTargetLowering()
182 if (!Subtarget.hasFSQRT() && in PPCTargetLowering()
183 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() && in PPCTargetLowering()
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DPPCAsmPrinter.cpp71 const PPCSubtarget *Subtarget; member in __anonfe451fe40111::PPCAsmPrinter
102 Subtarget = &MF.getSubtarget<PPCSubtarget>(); in runOnMachineFunction()
173 if (!Subtarget->isDarwin()) in printOperand()
289 if (!Subtarget->isDarwin()) in PrintAsmMemoryOperand()
394 int TOCSaveOffset = Subtarget->isELFv2ABI() ? 24 : 40; in LowerPATCHPOINT()
403 if (!Subtarget->isELFv2ABI()) { in LowerPATCHPOINT()
464 ((Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::X3) || in EmitTlsCall()
465 (!Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::R3)) && in EmitTlsCall()
468 ((Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::X3) || in EmitTlsCall()
469 (!Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::R3)) && in EmitTlsCall()
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/external/mesa3d/src/gallium/drivers/radeon/
DAMDILInstrInfo.td16 def HasHWDDiv : Predicate<"Subtarget.device()"
18 "Subtarget.device()->usesHardware(AMDGPUDeviceInfo::DoubleOps)">;
22 def HasSWDDiv : Predicate<"Subtarget.device()"
24 "Subtarget.device()->usesHardware(AMDGPUDeviceInfo::DoubleOps)">;
28 def HasHWSign24Bit : Predicate<"Subtarget.device()"
32 def HasHW64Bit : Predicate<"Subtarget.device()"
34 def HasSW64Bit : Predicate<"Subtarget.device()"
38 def HasTmrRegister : Predicate<"Subtarget.device()"
41 def HasDeviceIDInst : Predicate<"Subtarget.device()"
45 def hasRegionAS : Predicate<"Subtarget.device()"
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DAMDGPUTargetMachine.cpp49 Subtarget(TT, CPU, FS), in AMDGPUTargetMachine()
50 DataLayout(Subtarget.getDataLayout()), in AMDGPUTargetMachine()
52 Subtarget.device()->getStackAlignment(), 0), in AMDGPUTargetMachine()
54 InstrItins(&Subtarget.getInstrItineraryData()), in AMDGPUTargetMachine()
59 if (Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) { in AMDGPUTargetMachine()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp73 : TargetLowering(TM), Subtarget(&STI) { in X86TargetLowering()
74 X86ScalarSSEf64 = Subtarget->hasSSE2(); in X86TargetLowering()
75 X86ScalarSSEf32 = Subtarget->hasSSE1(); in X86TargetLowering()
88 if (Subtarget->isAtom()) in X86TargetLowering()
90 else if (Subtarget->is64Bit()) in X86TargetLowering()
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo(); in X86TargetLowering()
99 if (Subtarget->hasSlowDivide32()) in X86TargetLowering()
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit()) in X86TargetLowering()
105 if (Subtarget->isTargetKnownWindowsMSVC()) { in X86TargetLowering()
119 if (Subtarget->isTargetDarwin()) { in X86TargetLowering()
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DX86SelectionDAGInfo.cpp52 const X86Subtarget &Subtarget = in EmitTargetCodeForMemset() local
70 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) { in EmitTargetCodeForMemset()
75 V->isNullValue() ? Subtarget.getBZeroEntry() : nullptr) { in EmitTargetCodeForMemset()
125 if (Subtarget.is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned in EmitTargetCodeForMemset()
154 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, in EmitTargetCodeForMemset()
157 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI, in EmitTargetCodeForMemset()
204 const X86Subtarget &Subtarget = in EmitTargetCodeForMemcpy() local
209 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemcpy()
240 AVT = Subtarget.is64Bit() ? MVT::i64 : MVT::i32; in EmitTargetCodeForMemcpy()
248 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, in EmitTargetCodeForMemcpy()
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DX86FastISel.cpp51 const X86Subtarget *Subtarget; member in __anon71e944230111::X86FastISel
64 Subtarget = &funcInfo.MF->getSubtarget<X86Subtarget>(); in X86FastISel()
65 X86ScalarSSEf64 = Subtarget->hasSSE2(); in X86FastISel()
66 X86ScalarSSEf32 = Subtarget->hasSSE1(); in X86FastISel()
136 return Subtarget->getInstrInfo(); in getInstrInfo()
375 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm; in X86FastEmitLoad()
384 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm; in X86FastEmitLoad()
396 Opc = Subtarget->hasAVX() ? X86::VMOVAPSrm : X86::MOVAPSrm; in X86FastEmitLoad()
398 Opc = Subtarget->hasAVX() ? X86::VMOVUPSrm : X86::MOVUPSrm; in X86FastEmitLoad()
403 Opc = Subtarget->hasAVX() ? X86::VMOVAPDrm : X86::MOVAPDrm; in X86FastEmitLoad()
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/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.cpp57 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getReservedRegs() local
68 if (!Subtarget.is64Bit()) in getReservedRegs()
83 if (ReserveAppRegisters || !Subtarget.is64Bit()) in getReservedRegs()
91 if (!Subtarget.isV9()) { in getReservedRegs()
104 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getPointerRegClass() local
105 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in getPointerRegClass()
174 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in eliminateFrameIndex() local
183 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { in eliminateFrameIndex()
185 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
197 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
DDelaySlotFiller.cpp45 const SparcSubtarget *Subtarget; member
57 Subtarget = &F.getSubtarget<SparcSubtarget>(); in runOnMachineFunction()
110 Subtarget = &MBB.getParent()->getSubtarget<SparcSubtarget>(); in runOnMachineBasicBlock()
111 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); in runOnMachineBasicBlock()
127 if (!Subtarget->isV9() && in runOnMachineBasicBlock()
190 slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET)); in findDelayInstr()
332 for (MCRegAliasIterator AI(Reg, Subtarget->getRegisterInfo(), true); in IsRegInSet()
485 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); in tryCombineRestoreWithPrevInst()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp164 : TargetLowering(TM), Subtarget(&STI) { in ARMTargetLowering()
165 RegInfo = Subtarget->getRegisterInfo(); in ARMTargetLowering()
166 Itins = Subtarget->getInstrItineraryData(); in ARMTargetLowering()
170 if (Subtarget->isTargetMachO()) { in ARMTargetLowering()
172 if (Subtarget->isThumb() && Subtarget->hasVFP2() && in ARMTargetLowering()
173 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) { in ARMTargetLowering()
243 if (Subtarget->isTargetWatchOS()) { in ARMTargetLowering()
255 if (Subtarget->isAAPCS_ABI() && in ARMTargetLowering()
256 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() || in ARMTargetLowering()
257 Subtarget->isTargetAndroid())) { in ARMTargetLowering()
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DARMBaseInstrInfo.cpp97 Subtarget(STI) { in ARMBaseInstrInfo()
122 if (Subtarget.isThumb2() || Subtarget.hasVFP2()) in CreateTargetPostRAHazardRecognizer()
662 const ARMSubtarget &Subtarget) const { in copyFromCPSR()
663 unsigned Opc = Subtarget.isThumb() in copyFromCPSR()
664 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR) in copyFromCPSR()
672 if (Subtarget.isMClass()) in copyFromCPSR()
683 const ARMSubtarget &Subtarget) const { in copyToCPSR()
684 unsigned Opc = Subtarget.isThumb() in copyToCPSR()
685 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR) in copyToCPSR()
690 if (Subtarget.isMClass()) in copyToCPSR()
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DARMFastISel.cpp79 const ARMSubtarget *Subtarget; member in __anon68c1b2570111::ARMFastISel
94 Subtarget( in ARMFastISel()
97 TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()), in ARMFastISel()
98 TLI(*Subtarget->getTargetLowering()) { in ARMFastISel()
489 if (!Subtarget->hasVFP2()) return false; in ARMMaterializeFP()
517 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) { in ARMMaterializeInt()
529 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) { in ARMMaterializeInt()
546 if (Subtarget->useMovt(*FuncInfo.MF)) in ARMMaterializeInt()
584 bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM); in ARMMaterializeGV()
592 if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0; in ARMMaterializeGV()
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/external/llvm/lib/Target/BPF/
DBPFTargetMachine.h23 BPFSubtarget Subtarget; variable
30 const BPFSubtarget *getSubtargetImpl() const { return &Subtarget; } in getSubtargetImpl()
32 return &Subtarget; in getSubtargetImpl()
/external/llvm/lib/Target/XCore/
DXCoreTargetMachine.h24 XCoreSubtarget Subtarget; variable
32 const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; } in getSubtargetImpl()
34 return &Subtarget; in getSubtargetImpl()
/external/llvm/lib/Target/SystemZ/
DSystemZTargetMachine.h27 SystemZSubtarget Subtarget; variable
36 const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; } in getSubtargetImpl()
38 return &Subtarget; in getSubtargetImpl()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUTargetMachine.h36 AMDGPUSubtarget Subtarget; variable
45 const AMDGPUSubtarget *getSubtargetImpl() const { return &Subtarget; } in getSubtargetImpl()
47 return &Subtarget; in getSubtargetImpl()
/external/llvm/lib/Target/NVPTX/
DNVPTXTargetMachine.h31 NVPTXSubtarget Subtarget; variable
44 return &Subtarget; in getSubtargetImpl()
46 const NVPTXSubtarget *getSubtargetImpl() const { return &Subtarget; } in getSubtargetImpl()

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