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Searched defs:Opc (Results 1 – 25 of 146) sorted by relevance

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/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.h416 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode()
421 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
426 bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode()
432 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode()
436 static inline bool isPopOpcode(int Opc) { in isPopOpcode()
442 static inline bool isPushOpcode(int Opc) { in isPushOpcode()
DARMFastISel.cpp474 unsigned Opc; in ARMMaterializeFP() local
499 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP() local
518 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; in ARMMaterializeInt() local
534 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; in ARMMaterializeInt() local
598 unsigned Opc; in ARMMaterializeGV() local
636 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic; in ARMMaterializeGV() local
652 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD; in ARMMaterializeGV() local
717 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in fastMaterializeAlloca() local
895 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in ARMSimplifyAddress() local
960 unsigned Opc; in ARMEmitLoad() local
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DARMISelDAGToDAG.cpp119 SDValue &Opc) { in SelectAddrMode2Base()
124 SDValue &Opc) { in SelectAddrMode2ShOp()
129 SDValue &Opc) { in SelectAddrMode2()
312 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { in isOpcWithIntImmediate()
540 SDValue &Opc, in SelectImmShifterOperand()
582 SDValue &Opc, in SelectRegShifterOperand()
659 SDValue &Opc) { in SelectLdStSOReg()
770 SDValue &Opc) { in SelectAddrMode2Worker()
905 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetReg()
941 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetImmPre()
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DARMLoadStoreOptimizer.cpp349 static bool isT1i32Load(unsigned Opc) { in isT1i32Load()
353 static bool isT2i32Load(unsigned Opc) { in isT2i32Load()
357 static bool isi32Load(unsigned Opc) { in isi32Load()
361 static bool isT1i32Store(unsigned Opc) { in isT1i32Store()
365 static bool isT2i32Store(unsigned Opc) { in isT2i32Store()
369 static bool isi32Store(unsigned Opc) { in isi32Store()
373 static bool isLoadSingle(unsigned Opc) { in isLoadSingle()
377 static unsigned getImmScale(unsigned Opc) { in getImmScale()
450 unsigned Opc = MBBI->getOpcode(); in UpdateBaseRegUses() local
1016 static unsigned getUpdatingLSMultipleOpcode(unsigned Opc, in getUpdatingLSMultipleOpcode()
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/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.h241 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } in isUncondBranchOpcode()
243 static inline bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
260 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; } in isIndirectBranchOpcode()
DAArch64LoadStoreOptimizer.cpp149 static bool isUnscaledLdSt(unsigned Opc) { in isUnscaledLdSt()
195 static bool isNarrowStore(unsigned Opc) { in isNarrowStore()
211 static bool isNarrowLoad(unsigned Opc) { in isNarrowLoad()
289 static unsigned getMatchingNonSExtOpcode(unsigned Opc, in getMatchingNonSExtOpcode()
342 static unsigned getMatchingPairOpcode(unsigned Opc) { in getMatchingPairOpcode()
402 static unsigned getPreIndexedOpcode(unsigned Opc) { in getPreIndexedOpcode()
461 static unsigned getPostIndexedOpcode(unsigned Opc) { in getPostIndexedOpcode()
585 unsigned Opc = in mergePairedInsns() local
876 unsigned Opc = FirstMI->getOpcode(); in findMatchingInsn() local
1415 unsigned Opc = MI->getOpcode(); in optimizeBlock() local
DAArch64ConditionOptimizer.cpp199 static int getComplementOpc(int Opc) { in getComplementOpc()
226 unsigned Opc = CmpMI->getOpcode(); in adjustCmp() local
255 unsigned Opc; in modifyCmp() local
DAArch64InstrInfo.cpp304 unsigned Opc = 0; in canFoldIntoCSel() local
485 unsigned Opc = 0; in insertSelect() local
839 unsigned Opc = CmpInstr->getOpcode(); in optimizeCompareInstr() local
928 unsigned Opc = Instr.getOpcode(); in optimizeCompareInstr() local
1845 unsigned Opc = 0; in storeRegToStackSlot() local
1943 unsigned Opc = 0; in loadRegFromStackSlot() local
2049 unsigned Opc; in emitFrameOffset() local
2403 static bool isCombineInstrSettingFlag(unsigned Opc) { in isCombineInstrSettingFlag()
2422 static bool isCombineInstrCandidate32(unsigned Opc) { in isCombineInstrCandidate32()
2441 static bool isCombineInstrCandidate64(unsigned Opc) { in isCombineInstrCandidate64()
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DAArch64FastISel.cpp370 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi; in materializeFP() local
403 unsigned Opc = Is64Bit ? AArch64::LDRDui : AArch64::LDRSui; in materializeFP() local
491 unsigned Opc = Is64Bit ? AArch64::FMOVXDr : AArch64::FMOVWSr; in fastMaterializeFloatZero() local
1259 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_rr() local
1301 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_ri() local
1344 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_rs() local
1384 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_rx() local
1457 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri; in emitFCmp() local
1468 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr; in emitFCmp() local
1623 unsigned Opc; in emitLogicalOp_ri() local
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DAArch64BranchRelaxation.cpp284 static bool isConditionalBranch(unsigned Opc) { in isConditionalBranch()
319 static unsigned getOppositeConditionOpcode(unsigned Opc) { in getOppositeConditionOpcode()
335 static unsigned getBranchDisplacementBits(unsigned Opc) { in getBranchDisplacementBits()
DAArch64ISelDAGToDAG.cpp223 static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc, in isOpcWithIntImmediate()
1019 unsigned Opc, bool isExt) { in SelectTable()
1135 unsigned Opc, unsigned SubRegIdx) { in SelectLoad()
1156 unsigned Opc, unsigned SubRegIdx) { in SelectPostLoad()
1188 unsigned Opc) { in SelectStore()
1204 unsigned Opc) { in SelectPostStore()
1260 unsigned Opc) { in SelectLoadLane()
1300 unsigned Opc) { in SelectPostLoadLane()
1356 unsigned Opc) { in SelectStoreLane()
1386 unsigned Opc) { in SelectPostStoreLane()
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DAArch64AdvSIMDScalarPass.cpp172 static unsigned getTransformOpcode(unsigned Opc) { in getTransformOpcode()
193 unsigned Opc = MI->getOpcode(); in isTransformable() local
/external/llvm/lib/Target/Hexagon/
DHexagonCFGOptimizer.cpp58 static bool IsConditionalBranch(int Opc) { in IsConditionalBranch()
64 static bool IsUnconditionalJump(int Opc) { in IsUnconditionalJump()
111 int Opc = MI->getOpcode(); in runOnMachineFunction() local
DHexagonGenPredicate.cpp120 unsigned HexagonGenPredicate::getPredForm(unsigned Opc) { in getPredForm()
166 unsigned Opc = MI->getOpcode(); in isConvertibleToPredForm() local
190 unsigned Opc = MI->getOpcode(); in collectPredicateGPR() local
238 unsigned Opc = DefI->getOpcode(); in getPredRegFor() local
267 bool HexagonGenPredicate::isScalarCmp(unsigned Opc) { in isScalarCmp()
353 unsigned Opc = MI->getOpcode(); in convertToPredForm() local
DHexagonBitSimplify.cpp428 bool HexagonBitSimplify::getUsedBitsInStore(unsigned Opc, BitVector &Bits, in getUsedBitsInStore()
588 bool HexagonBitSimplify::getUsedBits(unsigned Opc, unsigned OpN, in getUsedBits()
957 unsigned Opc = MI->getOpcode(); in runOnNode() local
1036 unsigned Opc = MI.getOpcode(); in isLossyShiftLeft() local
1096 unsigned Opc = MI.getOpcode(); in isLossyShiftRight() local
1206 unsigned Opc = MI.getOpcode(); in computeUsedBits() local
1357 unsigned Opc = MI->getOpcode(); in isTfrConst() local
1393 unsigned Opc = isInt<8>(Lo) ? Hexagon::A2_combineii in genTfrConst() local
1407 unsigned Opc; in genTfrConst() local
1552 unsigned Opc = I->getOpcode(); in processBlock() local
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/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp43 unsigned Opc = MI->getOpcode(); in isLoadFromStackSlot() local
65 unsigned Opc = MI->getOpcode(); in isStoreToStackSlot() local
83 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
187 unsigned Opc = 0; in storeRegToStack() local
255 unsigned Opc = 0; in loadRegFromStack() local
331 unsigned Opc; in expandPostRAPseudo() local
515 MipsSEInstrInfo::compareOpndSize(unsigned Opc, in compareOpndSize()
DMips16InstrInfo.cpp65 unsigned Opc = 0; in copyPhysReg() local
102 unsigned Opc = 0; in storeRegToStack() local
120 unsigned Opc = 0; in loadRegFromStack() local
205 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16; in makeFrame() local
235 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? in restoreFrame() local
DMipsAnalyzeImmediate.h20 unsigned Opc, ImmOpnd; member
DMipsFastISel.cpp149 MachineInstrBuilder emitInst(unsigned Opc) { in emitInst()
152 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) { in emitInst()
156 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg, in emitInstStore()
160 MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg, in emitInstLoad()
238 unsigned Opc; in emitLogicalOp() local
308 unsigned Opc = Mips::ADDiu; in materialize32BitInt() local
659 unsigned Opc, CondMovOpc; in emitCmp() local
709 unsigned Opc; in emitLoad() local
770 unsigned Opc; in emitStore() local
1063 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32; in selectFPToInt() local
DMipsInstrInfo.cpp71 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, in AnalyzeCondBr()
100 unsigned Opc = Cond[0].getImm(); in BuildCondBr() local
/external/llvm/lib/Target/X86/
DX86FastISel.cpp351 unsigned Opc = 0; in X86FastEmitLoad() local
442 unsigned Opc = 0; in X86FastEmitStore() local
532 unsigned Opc = 0; in X86FastEmitStore() local
569 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend()
630 unsigned Opc = 0; in handleConstantAddresses() local
1318 unsigned Opc = X86::getSETFromCond(CC); in X86SelectCmp() local
1871 unsigned Opc = X86::getCMovFromCond(CC, RC->getSize()); in X86FastEmitCMoveSelect() local
1924 unsigned *Opc = nullptr; in X86FastEmitSSESelect() local
1990 unsigned Opc; in X86FastEmitPseudoSelect() local
2162 unsigned Opc = Subtarget->hasAVX() ? X86::VCVTSS2SDrr : X86::CVTSS2SDrr; in X86SelectFPExt() local
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DX86InstrInfo.cpp2540 unsigned Opc, bool AllowSP, in classifyLEAReg()
2626 unsigned Opc, leaInReg; in convertToThreeAddressWithLEA() local
2777 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; in convertToThreeAddress() local
2813 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r in convertToThreeAddress() local
2842 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r in convertToThreeAddress() local
2875 unsigned Opc; in convertToThreeAddress() local
2949 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; in convertToThreeAddress() local
3157 unsigned Opc; in commuteInstructionImpl() local
3295 unsigned Opc; in commuteInstructionImpl() local
3357 unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2); in commuteInstructionImpl() local
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DX86FrameLowering.cpp158 unsigned Opc = MBBI->getOpcode(); in findDeadCallerSavedReg() local
269 unsigned Opc = Is64Bit ? X86::MOV64ri : X86::MOV32ri; in emitSPUpdate() local
291 unsigned Opc = isSub in emitSPUpdate() local
354 unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset) in BuildStackAdjustment() local
374 unsigned Opc = PI->getOpcode(); in mergeSPUpdates() local
1338 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr; in emitPrologue() local
1526 unsigned Opc = PI->getOpcode(); in emitEpilogue() local
1586 unsigned Opc = getLEArOpcode(Uses64BitFramePtr); in emitEpilogue() local
1591 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr); in emitEpilogue() local
1873 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r; in spillCalleeSavedRegisters() local
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/external/llvm/lib/Target/AMDGPU/
DSILoadStoreOptimizer.cpp227 unsigned Opc = (EltSize == 4) ? AMDGPU::DS_READ2_B32 : AMDGPU::DS_READ2_B64; in mergeRead2Pair() local
323 unsigned Opc = (EltSize == 4) ? AMDGPU::DS_WRITE2_B32 : AMDGPU::DS_WRITE2_B64; in mergeWrite2Pair() local
394 unsigned Opc = MI.getOpcode(); in optimizeBlock() local
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp452 unsigned Opc; in PPCEmitLoad() local
609 unsigned Opc; in PPCEmitStore() local
1040 unsigned Opc; in SelectIToFP() local
1135 unsigned Opc; in SelectFPToI() local
1177 unsigned Opc; in SelectBinaryIntOp() local
1708 unsigned Opc; in PPCEmitIntExt() local
1902 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD; in PPCMaterializeFP() local
2100 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI; in PPCMaterializeInt() local
2106 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI; in PPCMaterializeInt() local
2255 unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) { in fastEmit_i()

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