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Searched refs:DefMI (Results 1 – 25 of 38) sorted by relevance

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/external/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp95 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI() local
97 if (DefMI->getParent() != MBB) in getAccDefMI()
99 if (DefMI->isCopyLike()) { in getAccDefMI()
100 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
102 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
105 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()
106 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
108 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
114 return DefMI; in getAccDefMI()
149 MachineInstr *DefMI = MRI->getVRegDef(Reg); in hasLoopHazard() local
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DARMHazardRecognizer.cpp19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, in hasRAWHazard() argument
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); in hasRAWHazard()
45 MachineInstr *DefMI = LastMI; in getHazardType() local
59 DefMI = &*I; in getHazardType()
63 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && in getHazardType()
65 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) { in getHazardType()
DARMBaseInstrInfo.cpp1891 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this); in optimizeSelect() local
1892 bool Invert = !DefMI; in optimizeSelect()
1893 if (!DefMI) in optimizeSelect()
1894 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this); in optimizeSelect()
1895 if (!DefMI) in optimizeSelect()
1908 DefMI->getDesc(), DestReg); in optimizeSelect()
1911 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect()
1914 NewMI.addOperand(DefMI->getOperand(i)); in optimizeSelect()
1937 SeenMIs.erase(DefMI); in optimizeSelect()
1943 if (DefMI->getParent() != MI->getParent()) in optimizeSelect()
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DARMBaseInstrInfo.h278 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
285 const MachineInstr *DefMI, unsigned DefIdx,
341 const MachineInstr *DefMI, unsigned DefIdx,
345 const MachineInstr *DefMI,
/external/llvm/lib/CodeGen/
DTargetSchedule.cpp155 const MachineInstr *DefMI, unsigned DefOperIdx, in computeOperandLatency() argument
159 return TII->defaultDefLatency(SchedModel, DefMI); in computeOperandLatency()
164 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, in computeOperandLatency()
168 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
175 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI); in computeOperandLatency()
183 TII->defaultDefLatency(SchedModel, DefMI)); in computeOperandLatency()
187 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency()
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency()
211 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit() in computeOperandLatency()
212 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
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DLiveRangeEdit.cpp52 const MachineInstr *DefMI, in checkRematerializable() argument
54 assert(DefMI && "Missing instruction"); in checkRematerializable()
56 if (!TII.isTriviallyReMaterializable(DefMI, aa)) in checkRematerializable()
66 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def); in scanRemattable() local
67 if (!DefMI) in scanRemattable()
69 checkRematerializable(VNI, DefMI, aa); in scanRemattable()
166 MachineInstr *DefMI = nullptr, *UseMI = nullptr; in foldAsLoad() local
172 if (DefMI && DefMI != MI) in foldAsLoad()
176 DefMI = MI; in foldAsLoad()
186 if (!DefMI || !UseMI) in foldAsLoad()
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DMachineTraceMetrics.cpp602 const MachineInstr *DefMI; member
606 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) in DataDep()
607 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep()
615 DefMI = DefI->getParent(); in DataDep()
761 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); in computeCrossBlockCriticalPath() local
763 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()]; in computeCrossBlockCriticalPath()
766 unsigned Len = LIR.Height + Cycles[DefMI].Depth; in computeCrossBlockCriticalPath()
834 BlockInfo[Dep.DefMI->getParent()->getNumber()]; in computeInstrDepths()
839 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth; in computeInstrDepths()
841 if (!Dep.DefMI->isTransient()) in computeInstrDepths()
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DInlineSpiller.cpp113 MachineInstr *DefMI; member
124 SpillReg(Reg), SpillVNI(VNI), SpillMBB(nullptr), DefMI(nullptr) {} in SibValueInfo()
127 bool hasDef() const { return DefByOrigPHI || DefMI; } in hasDef()
335 if (SVI.DefMI) in operator <<()
336 OS << " def: " << *SVI.DefMI; in operator <<()
399 DepSV.DefMI = SV.DefMI; in propagateSiblingValue()
500 return SVI->second.DefMI; in traceSiblingValue()
621 SVI->second.DefMI = MI; in traceSiblingValue()
642 return SVI->second.DefMI; in traceSiblingValue()
665 MachineInstr *DefMI = nullptr; in analyzeSiblingValues() local
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DRegisterCoalescer.cpp654 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); in removeCopyByCommutingDef() local
655 if (!DefMI) in removeCopyByCommutingDef()
657 if (!DefMI->isCommutable()) in removeCopyByCommutingDef()
661 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); in removeCopyByCommutingDef()
664 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) in removeCopyByCommutingDef()
677 if (!TII->findCommutedOpIndices(DefMI, UseOpIdx, NewDstIdx)) in removeCopyByCommutingDef()
680 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); in removeCopyByCommutingDef()
705 << *DefMI); in removeCopyByCommutingDef()
709 MachineBasicBlock *MBB = DefMI->getParent(); in removeCopyByCommutingDef()
711 TII->commuteInstruction(DefMI, false, UseOpIdx, NewDstIdx); in removeCopyByCommutingDef()
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DTargetInstrInfo.cpp1031 const MachineInstr *DefMI) const { in defaultDefLatency()
1032 if (DefMI->isTransient()) in defaultDefLatency()
1034 if (DefMI->mayLoad()) in defaultDefLatency()
1036 if (isHighLatencyDef(DefMI->getOpcode())) in defaultDefLatency()
1058 const MachineInstr *DefMI, in hasLowDefLatency() argument
1064 unsigned DefClass = DefMI->getDesc().getSchedClass(); in hasLowDefLatency()
1073 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency() argument
1075 unsigned DefClass = DefMI->getDesc().getSchedClass(); in getOperandLatency()
1084 const MachineInstr *DefMI) const { in computeDefOperandLatency()
1088 return getInstrLatency(ItinData, DefMI); in computeDefOperandLatency()
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DPHIElimination.cpp158 for (MachineInstr *DefMI : ImpDefs) { in runOnMachineFunction()
159 unsigned DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction()
162 LIS->RemoveMachineInstrFromMaps(DefMI); in runOnMachineFunction()
163 DefMI->eraseFromParent(); in runOnMachineFunction()
395 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) in LowerPHINode() local
396 if (DefMI->isImplicitDef()) in LowerPHINode()
397 ImpDefs.insert(DefMI); in LowerPHINode()
DMachineCSE.cpp133 MachineInstr *DefMI = MRI->getVRegDef(Reg); in INITIALIZE_PASS_DEPENDENCY() local
134 if (!DefMI->isCopy()) in INITIALIZE_PASS_DEPENDENCY()
136 unsigned SrcReg = DefMI->getOperand(1).getReg(); in INITIALIZE_PASS_DEPENDENCY()
139 if (DefMI->getOperand(0).getSubReg()) in INITIALIZE_PASS_DEPENDENCY()
153 if (DefMI->getOperand(1).getSubReg()) in INITIALIZE_PASS_DEPENDENCY()
158 DEBUG(dbgs() << "Coalescing: " << *DefMI); in INITIALIZE_PASS_DEPENDENCY()
165 DefMI->eraseFromParent(); in INITIALIZE_PASS_DEPENDENCY()
DTwoAddressInstructionPass.cpp318 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) { in getSingleDef()
319 if (DefMI.getParent() != BB || DefMI.isDebugValue()) in getSingleDef()
322 Ret = &DefMI; in getSingleDef()
323 else if (Ret != &DefMI) in getSingleDef()
447 MachineInstr *DefMI = &MI; in isKilled() local
453 if (!isPlainlyKilled(DefMI, Reg, LIS)) in isKilled()
462 DefMI = Begin->getParent(); in isKilled()
467 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) in isKilled()
987 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) { in isDefTooClose()
988 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike()) in isDefTooClose()
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DEarlyIfConversion.cpp245 MachineInstr *DefMI = MRI->getVRegDef(Reg); in canSpeculateInstrs() local
246 if (!DefMI || DefMI->getParent() != Head) in canSpeculateInstrs()
248 if (InsertAfter.insert(DefMI).second) in canSpeculateInstrs()
249 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI); in canSpeculateInstrs()
250 if (DefMI->isTerminator()) { in canSpeculateInstrs()
DMachineSink.cpp174 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in INITIALIZE_PASS_DEPENDENCY() local
175 if (DefMI->isCopyLike()) in INITIALIZE_PASS_DEPENDENCY()
177 DEBUG(dbgs() << "Coalescing: " << *DefMI); in INITIALIZE_PASS_DEPENDENCY()
393 MachineInstr *DefMI = MRI->getVRegDef(Reg); in isWorthBreakingCriticalEdge() local
394 if (DefMI->getParent() == MI->getParent()) in isWorthBreakingCriticalEdge()
/external/llvm/lib/Target/PowerPC/
DPPCMIPeephole.cpp124 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); in simplifyCode() local
128 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) { in simplifyCode()
129 unsigned FeedImmed = DefMI->getOperand(3).getImm(); in simplifyCode()
131 = lookThruCopyLike(DefMI->getOperand(1).getReg()); in simplifyCode()
133 = lookThruCopyLike(DefMI->getOperand(2).getReg()); in simplifyCode()
154 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg()); in simplifyCode()
155 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg()); in simplifyCode()
167 .addOperand(DefMI->getOperand(1)); in simplifyCode()
DPPCVSXSwapRemoval.cpp614 MachineInstr* DefMI = MRI->getVRegDef(Reg); in formWebs() local
615 assert(SwapMap.find(DefMI) != SwapMap.end() && in formWebs()
617 int DefIdx = SwapMap[DefMI]; in formWebs()
624 DEBUG(DefMI->dump()); in formWebs()
694 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs() local
695 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs()
705 DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
750 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in markSwapsForRemoval() local
751 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval()
755 DEBUG(DefMI->dump()); in markSwapsForRemoval()
DPPCInstrInfo.h120 const MachineInstr *DefMI, unsigned DefIdx,
131 const MachineInstr *DefMI, in hasLowDefLatency() argument
204 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
/external/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp132 for (auto DefMI : List) { in chooseBestLEA() local
136 if (!isSimilarMemOp(MI, MemOpNo, *DefMI, 1, AddrDispShiftTemp)) in chooseBestLEA()
149 MRI->getRegClass(DefMI->getOperand(0).getReg())) in chooseBestLEA()
156 int DistTemp = calcInstrDist(*DefMI, MI); in chooseBestLEA()
166 LEA = DefMI; in chooseBestLEA()
258 MachineInstr *DefMI; in removeRedundantAddrCalc() local
261 if (!chooseBestLEA(List, MI, DefMI, AddrDispShift, Dist)) in removeRedundantAddrCalc()
271 DefMI->removeFromParent(); in removeRedundantAddrCalc()
272 MBB->insert(MachineBasicBlock::iterator(&MI), DefMI); in removeRedundantAddrCalc()
276 MRI->clearKillFlags(DefMI->getOperand(0).getReg()); in removeRedundantAddrCalc()
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DX86CallFrameOptimization.cpp543 MachineBasicBlock::iterator DefMI = MRI->getVRegDef(Reg); in canFoldIntoRegPush() local
547 if (DefMI->getOpcode() != X86::MOV32rm || in canFoldIntoRegPush()
548 DefMI->getParent() != FrameSetup->getParent()) in canFoldIntoRegPush()
553 for (auto I = DefMI; I != FrameSetup; ++I) in canFoldIntoRegPush()
557 return DefMI; in canFoldIntoRegPush()
/external/llvm/lib/Target/Mips/
DMipsOptimizePICCall.cpp261 MachineInstr *DefMI = MRI.getVRegDef(Reg); in isCallViaRegister() local
263 assert(DefMI); in isCallViaRegister()
267 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3) in isCallViaRegister()
270 unsigned Flags = DefMI->getOperand(2).getTargetFlags(); in isCallViaRegister()
276 assert(DefMI->hasOneMemOperand()); in isCallViaRegister()
277 Val = (*DefMI->memoperands_begin())->getValue(); in isCallViaRegister()
279 Val = (*DefMI->memoperands_begin())->getPseudoValue(); in isCallViaRegister()
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h1122 MachineInstr *&DefMI) const { in optimizeLoadInstr() argument
1132 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, in FoldImmediate() argument
1165 const MachineInstr *DefMI, unsigned DefIdx,
1172 const MachineInstr *DefMI, unsigned DefIdx,
1190 const MachineInstr *DefMI) const;
1193 const MachineInstr *DefMI) const;
1206 const MachineInstr *DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
1215 const MachineInstr *DefMI, unsigned DefIdx) const;
/external/llvm/include/llvm/CodeGen/
DTargetSchedule.h162 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
184 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
DMachineTraceMetrics.h294 bool isDepInTrace(const MachineInstr *DefMI,
314 void addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp285 const MachineInstr *DefMI = MRI.getVRegDef(VReg); in removeCopies() local
286 if (!DefMI->isFullCopy()) in removeCopies()
288 VReg = DefMI->getOperand(1).getReg(); in removeCopies()
303 const MachineInstr *DefMI = MRI.getVRegDef(VReg); in canFoldIntoCSel() local
306 switch (DefMI->getOpcode()) { in canFoldIntoCSel()
310 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
316 if (!DefMI->getOperand(2).isImm() || DefMI->getOperand(2).getImm() != 1 || in canFoldIntoCSel()
317 DefMI->getOperand(3).getImm() != 0) in canFoldIntoCSel()
326 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); in canFoldIntoCSel()
337 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
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