| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 112 if (!RC || RC->isAllocatable()) in getAllocatableClass()
122 if (SubRC->isAllocatable()) in getAllocatableClass()
156 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); in getAllocatableSetForRC()
173 if ((*I)->isAllocatable()) in getAllocatableSet()
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| D | MachineRegisterInfo.cpp | 41 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); in setRegClass()
93 assert(RegClass->isAllocatable() && in createVirtualRegister()
425 if (!def_empty(*AI) || isAllocatable(*AI)) in isConstantPhysReg()
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| D | RegAllocFast.cpp | 527 !RC->contains(Hint) || !MRI->isAllocatable(Hint))) in allocVirtReg()
803 if (MRI->isAllocatable(LI.PhysReg)) in AllocateBasicBlock()
942 if (!MRI->isAllocatable(Reg)) continue; in AllocateBasicBlock()
1027 if (!MRI->isAllocatable(Reg)) continue; in AllocateBasicBlock()
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| D | CalcSpillWeights.cpp | 195 if (hweight > bestPhys && mri.isAllocatable(hint)) in calculateSpillWeightAndHint()
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| D | AggressiveAntiDepBreaker.cpp | 629 if (!MRI.isAllocatable(NewSuperReg)) continue; in FindSuitableFreeRegisters()
840 if (!MRI.isAllocatable(AntiDepReg)) { in BreakAntiDependencies()
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| D | MachineVerifier.cpp | 187 bool isAllocatable(unsigned Reg) { in isAllocatable() function
188 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg); in isAllocatable()
523 if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() && in visitMachineBasicBlockBefore()
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| D | CriticalAntiDepBreaker.cpp | 546 if (!MRI.isAllocatable(AntiDepReg)) in BreakAntiDependencies()
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| D | MachineCSE.cpp | 285 if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i])) in PhysRegDefsReach()
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| D | RegAllocPBQP.cpp | 426 if (!MF.getRegInfo().isAllocatable(DstReg)) in apply()
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| D | RegisterPressure.cpp | 380 } else if (MRI.isAllocatable(Reg)) { in pushRegUnits()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFrameLowering.cpp | 128 assert(MRI.isAllocatable(Reg)); in emitPrologue()
146 assert(MRI.isAllocatable(Reg) && in emitPrologue()
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| D | R600RegisterInfo.td | 159 let isAllocatable = 0 in {
205 } // End isAllocatable = 0
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 58 let isAllocatable = 0;
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 118 bool isAllocatable() const { return MC->isAllocatable(); } in isAllocatable() function
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| D | Target.td | 190 // isAllocatable - Specify that the register class can be used for virtual
192 // model instruction operand constraints, and should have isAllocatable = 0.
193 bit isAllocatable = 1;
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 248 let Size = 32, isAllocatable = 0 in
255 let Size = 64, isAllocatable = 0 in
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 443 let isAllocatable = 0;
457 let isAllocatable = 0;
461 let isAllocatable = 0;
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 95 bool isAllocatable() const { return Allocatable; } in isAllocatable() function
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 353 let isAllocatable = 0;
356 let isAllocatable = 0;
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| D | PPCRegisterInfo.cpp | 120 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); in getCalleeSavedRegs()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.td | 285 let isAllocatable = 0 in
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 709 bool isAllocatable(unsigned PhysReg) const { in isAllocatable() function
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 302 let isAllocatable = 0;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 26 bit isAllocatable = 0;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 265 let isAllocatable = 0;
|