| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 100 int shamt, int funct) { in EmitR() argument
108 shamt << kShamtShift | in EmitR()
114 int shamt, int funct) { in EmitRsd() argument
121 shamt << kShamtShift | in EmitRsd()
127 int shamt, int funct) { in EmitRtd() argument
134 shamt << kShamtShift | in EmitRtd()
476 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) { in Sll() argument
477 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00); in Sll()
480 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) { in Srl() argument
481 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x02); in Srl()
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| D | assembler_mips64.h | 489 void Sll(GpuRegister rd, GpuRegister rt, int shamt);
490 void Srl(GpuRegister rd, GpuRegister rt, int shamt);
491 void Rotr(GpuRegister rd, GpuRegister rt, int shamt);
492 void Sra(GpuRegister rd, GpuRegister rt, int shamt);
497 void Dsll(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
498 void Dsrl(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
499 void Drotr(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
500 void Dsra(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
501 void Dsll32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
502 void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
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| D | assembler_mips64_test.cc | 2661 void Dsll(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { in Dsll()
2662 regs_[rd] = regs_[rt] << (shamt & 0x1f); in Dsll()
2664 void Dsll32(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { in Dsll32()
2665 regs_[rd] = regs_[rt] << (32 + (shamt & 0x1f)); in Dsll32()
2667 void Dsrl(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { in Dsrl()
2668 regs_[rd] = regs_[rt] >> (shamt & 0x1f); in Dsrl()
2670 void Dsrl32(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { in Dsrl32()
2671 regs_[rd] = regs_[rt] >> (32 + (shamt & 0x1f)); in Dsrl32()
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 335 int shamt, in EmitR() argument
344 shamt << kShamtShift | in EmitR()
711 void MipsAssembler::Sll(Register rd, Register rt, int shamt) { in Sll() argument
712 CHECK(IsUint<5>(shamt)) << shamt; in Sll()
713 DsFsmInstrRrr(EmitR(0, static_cast<Register>(0), rt, rd, shamt, 0x00), rd, rt, rt); in Sll()
716 void MipsAssembler::Srl(Register rd, Register rt, int shamt) { in Srl() argument
717 CHECK(IsUint<5>(shamt)) << shamt; in Srl()
718 DsFsmInstrRrr(EmitR(0, static_cast<Register>(0), rt, rd, shamt, 0x02), rd, rt, rt); in Srl()
721 void MipsAssembler::Rotr(Register rd, Register rt, int shamt) { in Rotr() argument
722 CHECK(IsUint<5>(shamt)) << shamt; in Rotr()
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| D | assembler_mips.h | 260 void Sll(Register rd, Register rt, int shamt);
261 void Srl(Register rd, Register rt, int shamt);
262 void Rotr(Register rd, Register rt, int shamt); // R2+
263 void Sra(Register rd, Register rt, int shamt);
271 void ShiftAndAdd(Register dst, Register src_idx, Register src_base, int shamt, Register tmp = AT);
1469 uint32_t EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct);
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