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Searched refs:GPR32 (Results 1 – 23 of 23) sorted by relevance

/external/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td45 def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
47 (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
60 def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
62 (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
75 def : Pat<(relaxed_load<atomic_load_32> (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
77 (LDRWroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
90 def : Pat<(relaxed_load<atomic_load_64> (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
92 (LDRXroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
128 def : Pat<(releasing_store<atomic_store_8> GPR64sp:$ptr, GPR32:$val),
129 (STLRB GPR32:$val, GPR64sp:$ptr)>;
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DAArch64InstrInfo.td449 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
451 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
453 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
472 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
473 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
475 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
476 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
478 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
479 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
499 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
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DAArch64InstrFormats.td180 def GPR32as64 : RegisterOperand<GPR32> {
591 def arith_shifted_reg32 : arith_shifted_reg<i32, GPR32, 32>;
613 def logical_shifted_reg32 : logical_shifted_reg<i32, GPR32, logical_shift32>;
708 let MIOperandInfo = (ops GPR32, arith_extend);
714 let MIOperandInfo = (ops GPR32, arith_extend64);
1144 def W : BaseCmpBranch<GPR32, op, asm, node> {
1215 def W : BaseTestBranch<GPR32, tbz_imm0_31_diag, op, asm, node> {
1287 def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
1297 : BaseOneOperandData<opc, GPR32, asm, node> {
1341 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
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DAArch64RegisterInfo.td128 // GPR register classes with the intersections of GPR32/GPR32sp and
140 def GPR32 : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR)> {
141 let AltOrders = [(rotl GPR32, 8)];
606 [(rotl GPR32, 0), (rotl GPR32, 1)]>;
/external/llvm/test/CodeGen/Mips/
Ddivrem.ll3 …ify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,GPR32-TRAP
10 …mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,NOCHECK
19 ; GPR32 - GPR based multiply/divide on 32-bit targets
20 ; GPR64 - Same as GPR32 but only for 64-bit targets
23 ; GPR32-TRAP - Same as TRAP and GPR32 combined
40 ; GPR32: div $2, $4, $5
41 ; GPR32-TRAP: teq $5, $zero, 7
67 ; GPR32: mod $2, $4, $5
68 ; GPR32-TRAP: teq $5, $zero, 7
94 ; GPR32: divu $2, $4, $5
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZRegisterInfo.td24 // GPR32 - Lower 32 bits of one of the 16 64-bit general-purpose registers
25 class GPR32<bits<4> num, string n> : SystemZReg<n> {
64 def R0W : GPR32< 0, "r0">;
65 def R1W : GPR32< 1, "r1">;
66 def R2W : GPR32< 2, "r2">;
67 def R3W : GPR32< 3, "r3">;
68 def R4W : GPR32< 4, "r4">;
69 def R5W : GPR32< 5, "r5">;
70 def R6W : GPR32< 6, "r6">;
71 def R7W : GPR32< 7, "r7">;
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/external/llvm/lib/Target/Mips/
DMipsCondMov.td199 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
201 defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
202 defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>, INSN_MIPS4_32_NOT_32R6_64R6;
204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
206 defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>,
210 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
212 defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,
216 defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,
218 defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,
223 defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
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DMipsInstrInfo.td1618 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1619 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1620 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1621 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1622 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1623 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1624 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1625 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1626 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1627 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
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DMicroMipsInstrInfo.td113 let MIOperandInfo = (ops GPR32, simm11);
994 def : MipsPat<(not GPR32:$in),
999 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
1000 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
1001 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
1002 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
1006 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
1007 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
1011 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
1012 (SLL_MM GPR32:$src, immZExt5:$imm)>;
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DMips64InstrInfo.td331 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
333 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
586 def : MipsPat<(i64 (anyext GPR32:$src)),
587 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
588 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
589 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
DMipsDSPInstrInfo.td1306 def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
1317 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1318 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1319 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1320 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1327 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1329 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1422 DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1423 (Instr ACC64DSP:$ac, GPR32:$rs)>;
DMipsMSAInstrInfo.td3704 MipsPseudo<(outs GPR32:$dst),
3706 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3759 GPR32), (i32 24))>;
3764 GPR32), (i32 16))>;
3769 GPR32)>;
3780 GPR32), (i32 24))>;
3785 GPR32), (i32 16))>;
3790 GPR32)>;
3813 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3815 GPR32),
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DMicroMips32r6InstrInfo.td1739 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1740 (SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6;
1762 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
1763 (ANDI_MMR6 GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1768 def : MipsPat<(not GPR32:$in),
DMipsRegisterInfo.td292 def GPR32 : GPR32Class<[i32]>;
551 def GPR32Opnd : RegisterOperand<GPR32> {
DMips16InstrInfo.td291 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32),
299 FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz),
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dret.ll10 …=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,NO-MTHC1,NOT-R6
11 …rch=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
12 …rch=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
13 …rch=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
14 …-march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,R6C
113 ; GPR32-DAG: ori $3, $[[T0]], 1
114 ; GPR32-DAG: addiu $2, $zero, 0
128 ; GPR32-DAG: ori $2, $[[T0]], 1
129 ; GPR32-DAG: addiu $3, $zero, 0
142 ; GPR32-DAG: lui $[[T0:[0-9]+]], 1
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td58 class GPR32<bits<16> num, string n> : SystemZReg<n> {
63 class GPR64<bits<16> num, string n, GPR32 low, GPR32 high>
78 def R#I#L : GPR32<I, "r"#I>;
79 def R#I#H : GPR32<I, "r"#I>;
80 def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L"), !cast<GPR32>("R"#I#"H")>,
DSystemZFrameLowering.cpp122 unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32); in addSavedGPR() local
123 bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32); in addSavedGPR()
/external/llvm/test/CodeGen/AArch64/
Darm64-misched-memdep-bug.ll8 ; CHECK: SU(2): %vreg2<def> = LDRWui %vreg0, 1; mem:LD4[%ptr1_plus1] GPR32:%vreg2 GPR64common:%vr…
16 ; CHECK: SU(5): %W0<def> = COPY %vreg2; GPR32:%vreg2
Darm64-dead-register-def-bug.ll6 ; E.g. %X1<def, dead> = MOVi64imm 2, %W1<imp-def>; %X1:GPR64, %W1:GPR32
Ddp2.ll139 ; The point of this test is that we may not actually see (shl GPR32:$Val, (zext GPR32:$Val2))
Dbitfield.ll188 ; making sure that a 64-bit "(sext_inreg (anyext GPR32), i1)" uses the 64-bit
/external/llvm/test/CodeGen/Mips/msa/
D3r_splat.ll88 ; GPR32.