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Searched refs:InVec (Results 1 – 14 of 14) sorted by relevance

/external/llvm/test/Transforms/InstCombine/
Dvector-mul.ll6 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
8 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
15 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
17 %mul = mul <4 x i8> %InVec, <i8 1, i8 1, i8 1, i8 1>
22 ; CHECK: ret <4 x i8> %InVec
24 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
26 %mul = mul <4 x i8> %InVec, <i8 2, i8 2, i8 2, i8 2>
31 ; CHECK: shl <4 x i8> %InVec, <i8 1, i8 1, i8 1, i8 1>
34 define <4 x i8> @SplatPow2Test1_i8(<4 x i8> %InVec) {
36 %mul = mul <4 x i8> %InVec, <i8 4, i8 4, i8 4, i8 4>
[all …]
Dx86-pshufb.ll6 define <16 x i8> @identity_test(<16 x i8> %InVec) {
8 ; CHECK-NEXT: ret <16 x i8> %InVec
10 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 2…
14 define <32 x i8> @identity_test_avx2(<32 x i8> %InVec) {
16 ; CHECK-NEXT: ret <32 x i8> %InVec
18 …%1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 0, i8 1, i8 2, i8 …
24 define <16 x i8> @fold_to_zero_vector(<16 x i8> %InVec) {
28 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 -128…
32 define <32 x i8> @fold_to_zero_vector_avx2(<32 x i8> %InVec) {
36 …%1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 -128, i8 -128, i8 …
[all …]
/external/llvm/test/CodeGen/X86/
Dsse2-vector-shifts.ll6 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
11 %shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
15 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
21 %shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
25 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
31 %shl = shl <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
35 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
40 %shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
44 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
50 %shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
[all …]
Davx2-vector-shifts.ll6 define <16 x i16> @test_sllw_1(<16 x i16> %InVec) {
11 …%shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 …
15 define <16 x i16> @test_sllw_2(<16 x i16> %InVec) {
21 …%shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 …
25 define <16 x i16> @test_sllw_3(<16 x i16> %InVec) {
31 …%shl = shl <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16…
35 define <8 x i32> @test_slld_1(<8 x i32> %InVec) {
40 %shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
44 define <8 x i32> @test_slld_2(<8 x i32> %InVec) {
50 %shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp12182 SDValue InVec = N->getOperand(0); in visitINSERT_VECTOR_ELT() local
12189 return InVec; in visitINSERT_VECTOR_ELT()
12191 EVT VT = InVec.getValueType(); in visitINSERT_VECTOR_ELT()
12209 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() in visitINSERT_VECTOR_ELT()
12210 && isa<ConstantSDNode>(InVec.getOperand(2))) { in visitINSERT_VECTOR_ELT()
12212 cast<ConstantSDNode>(InVec.getOperand(2))->getZExtValue(); in visitINSERT_VECTOR_ELT()
12216 InVec.getOperand(0), InVal, EltNo); in visitINSERT_VECTOR_ELT()
12218 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()), in visitINSERT_VECTOR_ELT()
12219 VT, NewOp, InVec.getOperand(1), InVec.getOperand(2)); in visitINSERT_VECTOR_ELT()
12229 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
[all …]
DLegalizeVectorTypes.cpp1944 SDValue InVec = N->getOperand(0); in SplitVecOp_TruncateHelper() local
1945 EVT InVT = InVec->getValueType(0); in SplitVecOp_TruncateHelper()
1966 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL); in SplitVecOp_TruncateHelper()
2382 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops); in WidenVecRes_Convert() local
2384 return DAG.getNode(Opcode, DL, WidenVT, InVec); in WidenVecRes_Convert()
2385 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags); in WidenVecRes_Convert()
DSelectionDAGBuilder.cpp2980 SDValue InVec = getValue(I.getOperand(0)); in visitInsertElement() local
2986 InVec, InVal, InIdx)); in visitInsertElement()
2991 SDValue InVec = getValue(I.getOperand(0)); in visitExtractElement() local
2996 InVec, InIdx)); in visitExtractElement()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp6772 SDValue InVec = N->getOperand(0); in visitINSERT_VECTOR_ELT() local
6779 return InVec; in visitINSERT_VECTOR_ELT()
6781 EVT VT = InVec.getValueType(); in visitINSERT_VECTOR_ELT()
6796 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in visitINSERT_VECTOR_ELT()
6797 Ops.append(InVec.getNode()->op_begin(), in visitINSERT_VECTOR_ELT()
6798 InVec.getNode()->op_end()); in visitINSERT_VECTOR_ELT()
6799 } else if (InVec.getOpcode() == ISD::UNDEF) { in visitINSERT_VECTOR_ELT()
6825 SDValue InVec = N->getOperand(0); in visitEXTRACT_VECTOR_ELT() local
6827 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
6831 SDValue InOp = InVec.getOperand(0); in visitEXTRACT_VECTOR_ELT()
[all …]
DLegalizeVectorTypes.cpp1498 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, in WidenVecRes_Convert() local
1501 return DAG.getNode(Opcode, DL, WidenVT, InVec); in WidenVecRes_Convert()
1502 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1)); in WidenVecRes_Convert()
DSelectionDAGBuilder.cpp2756 SDValue InVec = getValue(I.getOperand(0)); in visitInsertElement() local
2763 InVec, InVal, InIdx)); in visitInsertElement()
2767 SDValue InVec = getValue(I.getOperand(0)); in visitExtractElement() local
2772 TLI.getValueType(I.getType()), InVec, InIdx)); in visitExtractElement()
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1997 SDValue InVec = N->getOperand(0); in PerformDAGCombine() local
2004 return InVec; in PerformDAGCombine()
2006 EVT VT = InVec.getValueType(); in PerformDAGCombine()
2021 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
2022 Ops.append(InVec.getNode()->op_begin(), in PerformDAGCombine()
2023 InVec.getNode()->op_end()); in PerformDAGCombine()
2024 } else if (InVec.isUndef()) { in PerformDAGCombine()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.cpp5373 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); in LowerMMXCONCAT_VECTORS() local
5374 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); in LowerMMXCONCAT_VECTORS()
5375 InVec = Op.getOperand(1); in LowerMMXCONCAT_VECTORS()
5376 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { in LowerMMXCONCAT_VECTORS()
5380 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); in LowerMMXCONCAT_VECTORS()
5382 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); in LowerMMXCONCAT_VECTORS()
5383 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); in LowerMMXCONCAT_VECTORS()
13133 SDValue InVec = ShAmtOp.getOperand(0); in PerformShiftCombine() local
13134 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in PerformShiftCombine()
13135 unsigned NumElts = InVec.getValueType().getVectorNumElements(); in PerformShiftCombine()
[all …]
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp19954 SDValue InVec = Amt.getOperand(0); in LowerScalarVariableShift() local
19955 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in LowerScalarVariableShift()
19956 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) && in LowerScalarVariableShift()
19958 BaseShAmt = InVec.getOperand(SplatIdx); in LowerScalarVariableShift()
19959 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { in LowerScalarVariableShift()
19961 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { in LowerScalarVariableShift()
19963 BaseShAmt = InVec.getOperand(1); in LowerScalarVariableShift()
19969 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec, in LowerScalarVariableShift()
26156 SDValue InVec = N->getOperand(0); in XFormVExtractWithShuffleIntoLoad() local
26163 EVT OriginalVT = InVec.getValueType(); in XFormVExtractWithShuffleIntoLoad()
[all …]
/external/llvm/lib/Transforms/Vectorize/
DSLPVectorizer.cpp2288 Value *InVec = vectorizeTree(INVL); in vectorizeTree() local
2294 Value *V = Builder.CreateCast(CI->getOpcode(), InVec, VecTy); in vectorizeTree()