| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 548 MCInst LEA; in LowerTlsAddr() local
550 LEA.setOpcode(X86::LEA64r); in LowerTlsAddr()
551 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest in LowerTlsAddr()
552 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base in LowerTlsAddr()
553 LEA.addOperand(MCOperand::CreateImm(1)); // scale in LowerTlsAddr()
554 LEA.addOperand(MCOperand::CreateReg(0)); // index in LowerTlsAddr()
555 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp in LowerTlsAddr()
556 LEA.addOperand(MCOperand::CreateReg(0)); // seg in LowerTlsAddr()
558 LEA.setOpcode(X86::LEA32r); in LowerTlsAddr()
559 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest in LowerTlsAddr()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86FixupLEAs.cpp | 253 static inline bool isLEASimpleIncOrDec(MachineInstr &LEA) { in isLEASimpleIncOrDec() argument
254 unsigned SrcReg = LEA.getOperand(1 + X86::AddrBaseReg).getReg(); in isLEASimpleIncOrDec()
255 unsigned DstReg = LEA.getOperand(0).getReg(); in isLEASimpleIncOrDec()
258 LEA.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isLEASimpleIncOrDec()
259 LEA.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 && in isLEASimpleIncOrDec()
260 LEA.getOperand(AddrDispOp).isImm() && in isLEASimpleIncOrDec()
261 (LEA.getOperand(AddrDispOp).getImm() == 1 || in isLEASimpleIncOrDec()
262 LEA.getOperand(AddrDispOp).getImm() == -1); in isLEASimpleIncOrDec()
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| D | X86MCInstLower.cpp | 725 MCInst LEA; in LowerTlsAddr() local
727 LEA.setOpcode(X86::LEA64r); in LowerTlsAddr()
728 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest in LowerTlsAddr()
729 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base in LowerTlsAddr()
730 LEA.addOperand(MCOperand::createImm(1)); // scale in LowerTlsAddr()
731 LEA.addOperand(MCOperand::createReg(0)); // index in LowerTlsAddr()
732 LEA.addOperand(MCOperand::createExpr(symRef)); // disp in LowerTlsAddr()
733 LEA.addOperand(MCOperand::createReg(0)); // seg in LowerTlsAddr()
735 LEA.setOpcode(X86::LEA32r); in LowerTlsAddr()
736 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest in LowerTlsAddr()
[all …]
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| /external/llvm/test/CodeGen/X86/ |
| D | overlap-shift.ll | 5 ;; allocator turns the shift into an LEA. This also occurs for ADD.
7 ; Check that the shift gets turned into an LEA.
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| D | add-nsw-sext.ll | 22 ; we allow LEA formation and eliminate an add instruction.
37 ; Throw in a scale (left shift) because an LEA can do that too.
38 ; Use a negative constant (LEA displacement) to verify that's handled correctly.
123 ; LEA can't scale by 16, but the adds can still be combined into an LEA.
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| D | atom-fixup-lea2.ll | 9 ; Test for fixup lea pre-emit pass. LEA instructions should be substituted for
11 ; precede the load within 5 instructions. An LEA should also be substituted for
12 ; an ADD which computes part of the index because it precedes the index LEA
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| D | twoaddr-lea.ll | 5 ;; allocator turns the shift into an LEA. This also occurs for ADD.
7 ; Check that the shift gets turned into an LEA.
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| D | mul-shift-reassoc.ll | 5 ; Push the shl through the mul to allow an LEA to be formed, instead
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| D | 2007-02-04-OrAddrMode.ll | 3 ;; This example can't fold the or into an LEA.
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| D | lea-opt.ll | 97 ; Check that LEA optimization pass takes into account a resultant address
98 ; displacement when choosing a LEA instruction for replacing a redundant
120 ; Make sure the REG3's definition LEA won't be removed as redundant.
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| D | stack-update-frame-opcode.ll | 11 ; Atoms use LEA to update the SP. Opcode bitness depends on data model.
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| D | lea-opt-memop-check-1.ll | 14 ; Check that the LEA optimization pass works with CPI address displacements.
57 ; Check that the LEA optimization pass works with MCSymbol address displacements.
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| D | or-lea.ll | 6 ; LEA instruction selection should be able to see through that
84 ; The shift is too big for an LEA.
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| D | merge-sp-update-lea.ll | 11 ; the LEA instruction.
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| D | atom-fixup-lea1.ll | 7 ; Test for the FixupLEAs pre-emit pass. An LEA should be substituted for the ADD
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| D | 3addr-or.ll | 29 ;; Test that OR is only emitted as LEA, not as ADD.
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| D | combine-multiplies.ll | 34 ; CHECK-NEXT: leal ([[ARG2:%[a-z]+]],[[MUL]]), [[LEA:%[a-z]+]]
35 ; CHECK-NEXT: movl $11, {{[0-9]+}}([[LEA]],[[ARG1]],4)
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| D | atom-fixup-lea3.ll | 6 ; An LEA should NOT be substituted for the ADD instruction
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| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | overlap-shift.ll | 5 ;; allocator turns the shift into an LEA. This also occurs for ADD.
7 ; Check that the shift gets turned into an LEA.
|
| D | twoaddr-lea.ll | 5 ;; allocator turns the shift into an LEA. This also occurs for ADD.
7 ; Check that the shift gets turned into an LEA.
|
| D | mul-shift-reassoc.ll | 5 ; Push the shl through the mul to allow an LEA to be formed, instead
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| D | 2007-02-04-OrAddrMode.ll | 3 ;; This example can't fold the or into an LEA.
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| D | 3addr-or.ll | 29 ;; Test that OR is only emitted as LEA, not as ADD.
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| D | 2010-06-25-CoalescerSubRegDefDead.ll | 21 ; statement. It can be an ADD or LEA instruction, it's not important which one
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | EDEmitter.cpp | 245 #define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress"); macro
314 LEA("lea32mem"); in X86TypeFromOpName()
315 LEA("lea64_32mem"); in X86TypeFromOpName()
316 LEA("lea64mem"); in X86TypeFromOpName()
339 #undef LEA
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