| /external/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 81 RCInfo &RCI = RegClass[RC->getID()]; in compute() local
86 if (!RCI.Order) in compute()
87 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
112 RCI.Order[N++] = PhysReg; in compute()
116 RCI.NumRegs = N + CSRAlias.size(); in compute()
117 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
125 RCI.Order[N++] = PhysReg; in compute()
130 if (StressRA && RCI.NumRegs > StressRA) in compute()
131 RCI.NumRegs = StressRA; in compute()
136 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
[all …]
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| D | TargetRegisterInfo.cpp | 217 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI) in getMatchingSuperRegClass() local
218 if (RCI.getSubReg() == Idx) in getMatchingSuperRegClass()
221 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this); in getMatchingSuperRegClass()
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| D | ShrinkWrap.cpp | 101 RegisterClassInfo RCI; member in __anone4a9c7fc0111::ShrinkWrap
161 RCI.runOnMachineFunction(MF); in init()
238 UseOrDefCSR = RCI.getLastCalleeSavedAlias(PhysReg); in INITIALIZE_PASS_DEPENDENCY()
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| D | PostRASchedulerList.cpp | 208 const RegisterClassInfo &RCI, in SchedulePostRATDList() argument
225 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) : in SchedulePostRATDList()
227 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : nullptr)); in SchedulePostRATDList()
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| D | AggressiveAntiDepBreaker.h | 128 const RegisterClassInfo &RCI,
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| D | RegisterPressure.cpp | 230 RCI = rci; in init()
920 const RegisterClassInfo *RCI, in computeExcessPressureDelta() argument
930 unsigned Limit = RCI->getRegPressureSetLimit(i); in computeExcessPressureDelta()
1064 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI, in getMaxUpwardPressureDelta()
1130 unsigned Limit = RCI->getRegPressureSetLimit(PSetID); in getUpwardPressureDelta()
1308 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI, in getMaxDownwardPressureDelta()
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| D | CriticalAntiDepBreaker.cpp | 31 const RegisterClassInfo &RCI) in CriticalAntiDepBreaker() argument
34 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker()
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| D | RegAllocGreedy.cpp | 122 RegisterClassInfo RCI; member in __anone3efcc7c0111::RAGreedy
1562 const RegisterClassInfo &RCI) { in getNumAllocatableRegsForConstraints() argument
1570 return RCI.getNumAllocatableRegs(ConstrainedRC); in getNumAllocatableRegsForConstraints()
1601 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
1611 TRI, RCI)) { in tryInstructionSplit()
2576 RCI.runOnMachineFunction(mf); in runOnMachineFunction()
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| D | TargetLoweringBase.cpp | 1271 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) in findRepresentativeClass() local
1272 SuperRegRC.setBitsInMask(RCI.getMask()); in findRepresentativeClass()
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| D | AggressiveAntiDepBreaker.cpp | 114 MachineFunction &MFi, const RegisterClassInfo &RCI, in AggressiveAntiDepBreaker() argument
118 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in AggressiveAntiDepBreaker()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 71 RCInfo &RCI = RegClass[RC->getID()]; in compute() local
76 if (!RCI.Order) in compute()
77 RCI.Order.reset(new unsigned[NumRegs]); in compute()
94 RCI.Order[N++] = PhysReg; in compute()
96 RCI.NumRegs = N + CSRAlias.size(); in compute()
97 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
100 std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]); in compute()
104 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
105 RCI.ProperSubClass = true; in compute()
109 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
[all …]
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| D | AllocationOrder.cpp | 28 : Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) { in AllocationOrder()
55 if (!RCI.isReserved(Order[i])) in AllocationOrder()
65 ArrayRef<unsigned> O = RCI.getOrder(RC); in AllocationOrder()
72 !RC->contains(Hint) || RCI.isReserved(Hint))) in AllocationOrder()
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| D | RegisterClassInfo.h | 65 const RCInfo &RCI = RegClass[RC->getID()]; in get() local
66 if (Tag != RCI.Tag) in get()
68 return RCI; in get()
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| D | AllocationOrder.h | 29 const RegisterClassInfo &RCI; variable
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| D | RegAllocLinearScan.cpp | 407 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(), in INITIALIZE_PASS_DEPENDENCY() local
408 E = tri_->regclass_end(); RCI != E; ++RCI) { in INITIALIZE_PASS_DEPENDENCY()
409 RelatedRegClasses.insert(*RCI); in INITIALIZE_PASS_DEPENDENCY()
410 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end(); in INITIALIZE_PASS_DEPENDENCY()
418 RelatedRegClasses.unionSets(PRC, *RCI); in INITIALIZE_PASS_DEPENDENCY()
420 PRC = *RCI; in INITIALIZE_PASS_DEPENDENCY()
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| D | PostRASchedulerList.cpp | 185 AliasAnalysis *AA, const RegisterClassInfo &RCI, in SchedulePostRATDList() argument
197 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) : in SchedulePostRATDList()
199 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : NULL)); in SchedulePostRATDList()
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| D | AggressiveAntiDepBreaker.h | 134 const RegisterClassInfo &RCI,
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| D | CriticalAntiDepBreaker.cpp | 30 CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI) : in CriticalAntiDepBreaker() argument
35 RegClassInfo(RCI), in CriticalAntiDepBreaker()
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| D | AggressiveAntiDepBreaker.cpp | 118 const RegisterClassInfo &RCI, in AggressiveAntiDepBreaker() argument
124 RegClassInfo(RCI), in AggressiveAntiDepBreaker()
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 71 const RCInfo &RCI = RegClass[RC->getID()]; in get() local
72 if (Tag != RCI.Tag) in get()
74 return RCI; in get()
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| D | RegisterPressure.h | 343 const RegisterClassInfo *RCI;
381 MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp),
385 MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp),
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| /external/llvm/lib/Transforms/Scalar/ |
| D | ConstantHoisting.cpp | 149 for (auto const &RCI : ConstInfo.RebasedConstants) in findConstantInsertionPoint() local
150 for (auto const &U : RCI.Uses) in findConstantInsertionPoint()
561 for (auto const &RCI : ConstInfo.RebasedConstants) { in emitBaseConstants() local
563 for (auto const &U : RCI.Uses) in emitBaseConstants()
564 emitBaseConstants(Base, RCI.Offset, U); in emitBaseConstants()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64A57FPLoadBalancing.cpp | 117 RegisterClassInfo RCI; member in __anon1c3805880111::AArch64A57FPLoadBalancing
326 RCI.runOnMachineFunction(F); in runOnMachineFunction()
534 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2757 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), in getRegForInlineAsmConstraint() local
2758 E = RI->regclass_end(); RCI != E; ++RCI) { in getRegForInlineAsmConstraint()
2759 const TargetRegisterClass *RC = *RCI; in getRegForInlineAsmConstraint()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2357 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), in getRegForInlineAsmConstraint() local
2358 E = RI->regclass_end(); RCI != E; ++RCI) { in getRegForInlineAsmConstraint()
2359 const TargetRegisterClass *RC = *RCI; in getRegForInlineAsmConstraint()
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