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Searched refs:isUInt (Results 1 – 25 of 89) sorted by relevance

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/external/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCCodeEmitter.cpp153 assert(isUInt<4>(Base) && isUInt<12>(Disp)); in getBDAddr12Encoding()
163 assert(isUInt<4>(Base) && isInt<20>(Disp)); in getBDAddr20Encoding()
174 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index)); in getBDXAddr12Encoding()
185 assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index)); in getBDXAddr20Encoding()
197 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len)); in getBDLAddr12Len8Encoding()
208 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<5>(Index)); in getBDVAddr12Encoding()
/external/llvm/lib/Target/SystemZ/
DSystemZTargetTransformInfo.cpp54 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost()
105 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost()
113 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost()
116 if (isUInt<32>(-Imm.getSExtValue())) in getIntImmCost()
131 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost()
144 if (isUInt<32>(~Imm.getZExtValue())) in getIntImmCost()
206 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost()
208 if (isUInt<32>(-Imm.getSExtValue())) in getIntImmCost()
DSystemZOperands.td282 return isUInt<1>(N->getZExtValue());
286 return isUInt<2>(N->getZExtValue());
290 return isUInt<3>(N->getZExtValue());
294 return isUInt<4>(N->getZExtValue());
300 return isUInt<4>(N->getZExtValue());
304 return isUInt<6>(N->getZExtValue());
312 return isUInt<8>(N->getZExtValue());
318 return isUInt<12>(N->getZExtValue());
326 return isUInt<16>(N->getZExtValue());
405 return isUInt<8>(N->getSExtValue());
[all …]
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParserCommon.h19 (isUInt<16>(Value) && isInt<8>(static_cast<int16_t>(Value))); in isImmSExti16i8Value()
24 (isUInt<32>(Value) && isInt<8>(static_cast<int32_t>(Value))); in isImmSExti32i8Value()
36 return isUInt<8>(Value) || isInt<8>(Value); in isImmUnsignedi8Value()
/external/llvm/lib/Target/AMDGPU/
DSILoadStoreOptimizer.cpp146 if (isUInt<8>(EltOffset0) && isUInt<8>(EltOffset1)) in offsetsCanBeCombined()
154 return isUInt<8>(EltOffset0 / 64) && isUInt<8>(EltOffset1 / 64); in offsetsCanBeCombined()
223 assert((isUInt<8>(NewOffset0) && isUInt<8>(NewOffset1)) && in mergeRead2Pair()
319 assert((isUInt<8>(NewOffset0) && isUInt<8>(NewOffset1)) && in mergeWrite2Pair()
DAMDGPUISelDAGToDAG.cpp643 if ((OffsetBits == 16 && !isUInt<16>(Offset)) || in isDSOffsetLegal()
644 (OffsetBits == 8 && !isUInt<8>(Offset))) in isDSOffsetLegal()
673 if (isUInt<16>(ByteOffset)) { in SelectDS1Addr1Offset()
701 if (isUInt<16>(CAddr->getZExtValue())) { in SelectDS1Addr1Offset()
742 if (isUInt<8>(DWordOffset0)) { in SelectDS64Bit4ByteAligned()
769 if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) { in SelectDS64Bit4ByteAligned()
789 return isUInt<12>(Imm->getZExtValue()); in isLegalMUBUFImmOffset()
839 if (isUInt<32>(C1->getZExtValue())) { in SelectMUBUF()
1085 isUInt<8>(EncodedOffset) : isUInt<20>(EncodedOffset); in isLegalSMRDImmOffset()
1108 if (!isUInt<32>(EncodedOffset) || !isUInt<32>(ByteOffset)) in SelectSMRDOffset()
[all …]
DSIRegisterInfo.cpp331 if (isUInt<12>(NewOffset)) { in resolveFrameIndex()
364 return SIInstrInfo::isMUBUF(*MI) && isUInt<12>(Offset); in isFrameOffsetLegal()
436 if (!isUInt<12>(Offset + Size)) { in buildScratchLoadStore()
/external/llvm/lib/Target/Hexagon/
DHexagonOperands.td221 return isUInt<32>(v);
226 return isUInt<32>(v);
251 return isUInt<16>(v);
271 return isUInt<10>(v);
276 return isUInt<9>(v);
281 return isUInt<8>(v);
287 return isUInt<7>(Imm) && Imm > 0;
292 return isUInt<7>(v);
297 return isUInt<6>(v);
302 return isUInt<6>(v);
[all …]
DHexagonInstrInfo.cpp2709 return isUInt<10>(Offset); in isValidOffset()
2788 return isUInt<6>(Offset); in isValidOffset()
3335 ((isUInt<5>(MI->getOperand(2).getImm())) || in getCompoundCandidateGroup()
3672 MI->getOperand(2).isImm() && isUInt<4>(MI->getOperand(2).getImm())) in getDuplexCandidateGroup()
3701 isUInt<3>(MI->getOperand(2).getImm())) in getDuplexCandidateGroup()
3780 MI->getOperand(1).isImm() && isUInt<4>(MI->getOperand(1).getImm())) in getDuplexCandidateGroup()
3816 MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm())) in getDuplexCandidateGroup()
3823 MI->getOperand(1).isImm() && isUInt<4>(MI->getOperand(1).getImm()) && in getDuplexCandidateGroup()
3824 MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm())) in getDuplexCandidateGroup()
3928 MI->getOperand(2).isImm() && isUInt<2>(MI->getOperand(2).getImm())) in getDuplexCandidateGroup()
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/Support/
DMathExtras.h56 inline bool isUInt(uint64_t x) { in isUInt() function
61 inline bool isUInt<8>(uint64_t x) {
65 inline bool isUInt<16>(uint64_t x) {
69 inline bool isUInt<32>(uint64_t x) {
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp453 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } in isU1Imm()
454 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } in isU2Imm()
455 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } in isU3Imm()
456 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } in isU4Imm()
457 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } in isU5Imm()
459 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } in isU6Imm()
461 isUInt<6>(getImm()) && in isU6ImmX2()
463 bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); } in isU7Imm()
465 isUInt<7>(getImm()) && in isU7ImmX4()
467 bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); } in isU8Imm()
[all …]
/external/swiftshader/third_party/llvm-subzero/include/llvm/Support/
DMathExtras.h298 isUInt(uint64_t X) {
304 isUInt(uint64_t X) {
309 template <> constexpr inline bool isUInt<8>(uint64_t x) {
312 template <> constexpr inline bool isUInt<16>(uint64_t x) {
315 template <> constexpr inline bool isUInt<32>(uint64_t x) {
328 return isUInt<N + S>(x) && (x % (UINT64_C(1) << S) == 0);
/external/llvm/include/llvm/Support/
DMathExtras.h291 inline bool isUInt(uint64_t x) {
296 inline bool isUInt<8>(uint64_t x) {
300 inline bool isUInt<16>(uint64_t x) {
304 inline bool isUInt<32>(uint64_t x) {
312 return isUInt<N+S>(x) && (x % (1<<S) == 0);
/external/llvm/lib/IR/
DDataLayout.cpp254 if (!isUInt<24>(AddrSpace)) in parseSpecifier()
400 if (!isUInt<24>(bit_width)) in setAlignment()
402 if (!isUInt<16>(abi_align)) in setAlignment()
404 if (!isUInt<16>(pref_align)) in setAlignment()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinRegisterInfo.cpp132 if (isUInt<16>(value)) { in loadConstant()
225 if (isUInt<6>(Offset)) { in eliminateFrameIndex()
231 if (BaseReg == BF::FP && isUInt<7>(-Offset)) { in eliminateFrameIndex()
DBlackfinInstrInfo.td68 def uimm3 : PatLeaf<(imm), [{return isUInt<3>(N->getZExtValue());}]>;
69 def uimm4 : PatLeaf<(imm), [{return isUInt<4>(N->getZExtValue());}]>;
70 def uimm5 : PatLeaf<(imm), [{return isUInt<5>(N->getZExtValue());}]>;
74 return value % 2 == 0 && isUInt<5>(value);
79 return value % 4 == 0 && isUInt<6>(value);
84 def uimm16 : PatLeaf<(imm), [{return isUInt<16>(N->getZExtValue());}]>;
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.cpp171 if (isUInt<6>(Offset)) { in eliminateFrameIndex()
233 assert(isUInt<6>(Offset) && "Offset is out of range"); in eliminateFrameIndex()
/external/llvm/lib/MC/
DMCCodeView.cpp207 if (isUInt<7>(Data)) { in compressAnnotation()
212 if (isUInt<14>(Data)) { in compressAnnotation()
218 if (isUInt<29>(Data)) { in compressAnnotation()
/external/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp223 bool isOffset() const { return isImmTy(ImmTyOffset) && isUInt<16>(getImm()); } in isOffset()
224 bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<16>(getImm()); } in isOffset0()
225 bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); } in isOffset1()
981 if (!isInt<32>(IntVal) && !isUInt<32>(IntVal)) { in parseImm()
1865 if (Imm16Val < 0 || !isUInt<16>(Imm16Val)) { in parseHwreg()
1878 if (HwReg.Id < 0 || !isUInt<ID_WIDTH_>(HwReg.Id)) { in parseHwreg()
1884 if (Offset < 0 || !isUInt<OFFSET_WIDTH_>(Offset)) in parseHwreg()
1886 if ((Width-1) < 0 || !isUInt<WIDTH_M1_WIDTH_>(Width-1)) in parseHwreg()
2014 if (Imm16Val < 0 || !isUInt<16>(Imm16Val)) { in parseSendMsgOp()
2273 return isImm() && isUInt<8>(getImm()); in isSMRDOffset()
[all …]
/external/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp155 if (!isUInt<N>(Imm)) in decodeUImmOperand()
163 if (!isUInt<N>(Imm)) in decodeSImmOperand()
240 assert(isUInt<N>(Imm) && "Invalid PC-relative offset"); in decodePCDBLOperand()
/external/llvm/include/llvm/ADT/
DPointerEmbeddedInt.h65 : llvm::isUInt<Bits>(I)) &&
/external/jsoncpp/src/lib_json/
Djson_value.cpp578 JSON_ASSERT_MESSAGE(isUInt(), "LargestInt out of UInt range"); in asUInt()
581 JSON_ASSERT_MESSAGE(isUInt(), "LargestUInt out of UInt range"); in asUInt()
734 return isUInt() || in isConvertibleTo()
1111 bool Value::isUInt() const { in isUInt() function in Json::Value
1170 return isInt() || isUInt(); in isIntegral()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp456 if (isUInt<16>(Imm)) in SelectCC()
480 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm)) in SelectCC()
497 if (isUInt<16>(Imm)) in SelectCC()
514 if (isUInt<32>(Imm)) { in SelectCC()
523 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm)) in SelectCC()
/external/llvm/lib/Target/Mips/
DMips16ISelLowering.cpp742 if (isUInt<8>(imm)) in emitFEXT_T8I8I16_ins()
744 else if ((!ImmSigned && isUInt<16>(imm)) || in emitFEXT_T8I8I16_ins()
757 if (isUInt<8>(Imm)) in Mips16WhichOp8uOr16simm()
DMips16InstrInfo.cpp209 if (isUInt<11>(FrameSize)) in makeFrame()
236 if (!isUInt<11>(FrameSize)) { in restoreFrame()

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