| /arch/blackfin/kernel/ |
| D | fixed_code.S | 21 P0 = __NR_rt_sigreturn; define
35 R0 = [P0];
36 [P0] = R1;
51 R0 = [P0];
54 [P0] = R2;
68 R1 = [P0];
70 [P0] = R0;
83 R1 = [P0];
85 [P0] = R0;
98 R1 = [P0];
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| /arch/blackfin/mach-common/ |
| D | dpmc_modes.S | 23 P0.H = hi(PLL_CTL);
24 P0.L = lo(PLL_CTL);
25 R1 = W[P0](z);
27 W[P0] = R1.L;
42 P0.H = hi(PLL_CTL);
43 P0.L = lo(PLL_CTL);
71 P0.H = hi(VR_CTL);
72 P0.L = lo(VR_CTL);
74 W[P0] = R3.L;
101 P0.H = hi(PLL_DIV);
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| D | cache.S | 46 P0 = R0; define
50 \optflushins [P0];
56 \flushins [P0++];
61 2: \flushins [P0++];
78 P0 = R0; define
79 IFLUSH[P0];
94 P0 = R0; define
95 IFLUSH[P0];
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| D | lock.S | 195 P0.L = LO(IMEM_CONTROL);
196 P0.H = HI(IMEM_CONTROL);
197 R7 = [P0];
206 [P0] = R7;
217 [P0] = R7;
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| D | head.S | 55 P0 = R0; define
96 P0 = R1; define
121 [P0] = R0;
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| D | entry.S | 1000 [sp + PT_RESERVED] = P0;
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| /arch/blackfin/lib/ |
| D | outs.S | 35 P0 = R0; /* P0 = port */ define
41 .Llong_loop_e: [P0] = R0;
46 P0 = R0; /* P0 = port */ define
52 .Lword_loop_e: W[P0] = R0;
57 P0 = R0; /* P0 = port */ define
63 .Lbyte_loop_e: B[P0] = R0;
68 P0 = R0; /* P0 = port */ define
77 .Lword8_loop_e: W[P0] = R0;
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| D | memcpy.S | 58 P0 = R0 ; /* dst*/ define
89 B[P0++] = R3;
101 [P0++] = R3;
107 MNOP || [P0++] = R3 || R3 = [I1++];
109 [P0++] = R3;
124 B[P0++] = R1;
135 P0 = P0 + P2; define
136 P0 += -1;
143 B[P0--] = R1;
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| D | memset.S | 49 P0 = R0 ; /* P0 = address */ define
69 [P0++] = R2;
71 CC = P0 == P2;
77 R3 = P0; /* current position */
88 B[P0++] = R1;
98 R0 = P0; /* Recover return address */
100 B[P0++] = R1;
105 B[P0++] = R1;
106 B[P0++] = R1;
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| D | memmove.S | 44 P0 = R0; /* P0 = To address */ define
75 [P0++] = R1;
81 MNOP || [P0++] = R1 || R1 = [I0++];
83 [P0++] = R1;
93 .Lbyte2_e: B[P0++] = R1;
100 P0 = P0 + P2; define
110 .Lol_s: B[P0--] = R1;
112 .Lno_loop: B[P0] = R1;
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| D | ins.S | 76 P0 = R0; /* P0 = port */ \
92 R0 = [P0]; \
97 R0 = W[P0]; \
102 R0 = W[P0]; \
109 R0 = B[P0]; \
114 R0 = [P0]; \
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| D | memcmp.S | 46 P0 = R0; /* P0 = s1 address */ define
65 R0 = [P0++];
68 MNOP || R0 = [P0++] || R1 = [I0++];
84 R0 = B[P0++](Z); /* *s1 */
104 P0 += -4; /* back up to the start of the */
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| D | memchr.S | 45 P0 = R0; /* P0 = address */ define
55 R3 = B[P0++](Z);
66 R0 = P0;
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| D | udivsi3.S | 156 P0 = 0; define
162 IF CC P0 = R6; /* Number of values divided */
187 CC = P0 == 0; /* Check how many inputs we shifted */
190 CC = P0 == 1;
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| /arch/blackfin/include/asm/ |
| D | dpmc.h | 31 R0 = [P0 + (x - SRAM_BASE_ADDRESS)];\
36 [P0 + (x - SRAM_BASE_ADDRESS)] = R0;\
39 R0 = [P0 + (x - PLL_CTL)];\
44 [P0 + (x - PLL_CTL)] = R0;\
47 R0 = w[P0 + (x - PLL_CTL)];\
52 w[P0 + (x - PLL_CTL)] = R0;\
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| D | entry.h | 32 P0.l = lo(IPEND); \
33 P0.h = hi(IPEND); \
34 R1 = [P0];
41 [--sp] = P0; /*orig_p0*/ \
53 [--sp] = P0; /*orig_p0*/ \
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| D | context.S | 43 [--sp] = P0; /*orig_p0*/
111 [--sp] = P0; /*orig_p0*/
170 [--sp] = P0; /* orig_p0 */
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| /arch/blackfin/mach-bf561/ |
| D | secondary.S | 51 P0 = R0; define
121 [P0] = R0;
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| /arch/cris/arch-v10/kernel/ |
| D | kgdb.c | 386 P0, VR, P2, P3, enumerator
566 else if (regno == P0 || regno == VR || regno == P4 || regno == P8) { in write_register()
636 else if (regno == P0 || regno == VR) { in read_register()
639 ((char *)&(current_reg->p0) + (regno-P0) * sizeof(char))); in read_register()
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| /arch/frv/kernel/ |
| D | sleep.S | 159 # - At this time, also set the CLKC register P0 bit.
340 # - At this time, also set the CLKC register P0 bit.
|