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Searched refs:bfin_write32 (Results 1 – 24 of 24) sorted by relevance

/arch/blackfin/include/asm/
Dcdef_LPBlackfin.h40 #define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
42 #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
44 #define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
46 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val)
51 #define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val)
53 #define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val)
55 #define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val)
57 #define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val)
59 #define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val)
61 #define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val)
[all …]
Ddef_LPBlackfin.h96 #define bfin_write32(addr, val) \ macro
/arch/blackfin/mach-bf518/include/mach/
DcdefBF516.h51 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
53 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
55 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
57 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
59 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
61 #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
63 #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
65 #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
67 #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
69 #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
[all …]
DcdefBF518.h52 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
54 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
56 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
58 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
60 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
62 #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
64 #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
66 #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
68 #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
70 #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
[all …]
DcdefBF51x_base.h53 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
63 #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
65 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
67 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
70 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
72 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
74 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
76 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
79 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
81 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
[all …]
/arch/blackfin/mach-bf537/include/mach/
DcdefBF537.h44 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE,val)
46 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO,val)
48 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI,val)
50 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO,val)
52 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI,val)
54 #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD,val)
56 #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT,val)
58 #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC,val)
60 #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1,val)
62 #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2,val)
[all …]
DcdefBF534.h60 #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val)
62 #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
64 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
66 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
68 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
70 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
72 #define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
74 #define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
80 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
82 #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
[all …]
/arch/blackfin/mach-bf538/include/mach/
DcdefBF539.h16 #define bfin_write_MXVR_PLL_CTL_0(val) bfin_write32(MXVR_PLL_CTL_0, val)
18 #define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
20 #define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
22 #define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
24 #define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
26 #define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
28 #define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
38 #define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
42 #define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
44 #define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
[all …]
DcdefBF538.h42 #define bfin_writePTR(addr, val) bfin_write32(addr, val)
53 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
61 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
63 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
65 #define bfin_write_SIC_IMASK(x, val) bfin_write32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0), val)
67 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
69 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
71 #define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)
73 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
75 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
[all …]
/arch/blackfin/mach-bf561/include/mach/
DcdefBF561.h71 #define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val)
73 #define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val)
75 #define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val)
77 #define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val)
79 #define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val)
81 #define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val)
83 #define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val)
85 #define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val)
87 #define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val)
89 #define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val)
[all …]
Dblackfin.h68 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
70 #define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val)
72 #define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
74 #define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val)
/arch/blackfin/mach-bf533/include/mach/
DcdefBF532.h59 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
61 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
63 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
65 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
67 #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
69 #define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
71 #define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
77 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
79 #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
83 #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
[all …]
/arch/blackfin/mach-bf527/include/mach/
DcdefBF52x_base.h53 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
63 #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
65 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
67 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
70 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
72 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
74 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
76 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
79 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
81 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
[all …]
DcdefBF527.h51 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
53 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
55 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
57 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
59 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
61 #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
63 #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
65 #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
67 #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
69 #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
[all …]
/arch/blackfin/mach-bf548/include/mach/
DcdefBF54x_base.h56 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
68 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
70 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
72 #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
74 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
77 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
79 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
81 #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
83 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
86 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
[all …]
DcdefBF549.h52 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
54 #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
56 #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
60 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
62 #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
64 #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
68 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
70 #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
72 #define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
81 #define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
[all …]
DcdefBF547.h52 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
54 #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
56 #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
60 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
62 #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
64 #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
68 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
70 #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
72 #define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
81 #define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
[all …]
DcdefBF548.h52 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
54 #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
56 #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
60 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
62 #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
64 #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
68 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
70 #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
72 #define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
81 #define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
[all …]
DcdefBF544.h52 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
54 #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
56 #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
60 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
62 #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
64 #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
68 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
70 #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
72 #define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
81 #define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
[all …]
DcdefBF542.h107 #define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
113 #define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
115 #define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
117 #define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
119 #define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
121 #define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
129 #define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
133 #define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
135 #define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
139 #define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
/arch/blackfin/kernel/cplb-mpu/
Dcacheinit.c35 bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr); in bfin_icache_init()
36 bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data); in bfin_icache_init()
53 bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr); in bfin_dcache_init()
54 bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data); in bfin_dcache_init()
Dcplbmgr.c198 bfin_write32(DCPLB_DATA0 + idx * 4, d_data); in dcplb_miss()
199 bfin_write32(DCPLB_ADDR0 + idx * 4, addr); in dcplb_miss()
285 bfin_write32(ICPLB_DATA0 + idx * 4, i_data); in icplb_miss()
286 bfin_write32(ICPLB_ADDR0 + idx * 4, addr); in icplb_miss()
305 bfin_write32(DCPLB_DATA0 + idx * 4, data); in dcplb_protection_fault()
339 bfin_write32(ICPLB_DATA0 + i * 4, 0); in flush_switched_cplbs()
346 bfin_write32(DCPLB_DATA0 + i * 4, 0); in flush_switched_cplbs()
380 bfin_write32(DCPLB_DATA0 + i * 4, d_data); in set_mask_dcplbs()
381 bfin_write32(DCPLB_ADDR0 + i * 4, addr); in set_mask_dcplbs()
/arch/blackfin/kernel/cplb-nompu/
Dcacheinit.c35 bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr); in bfin_icache_init()
36 bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data); in bfin_icache_init()
53 bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr); in bfin_dcache_init()
54 bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data); in bfin_dcache_init()
Dcplbmgr.c77 bfin_write32(DCPLB_DATA0 + idx * 4, data); in write_dcplb_data()
78 bfin_write32(DCPLB_ADDR0 + idx * 4, addr); in write_dcplb_data()
93 bfin_write32(ICPLB_DATA0 + idx * 4, data); in write_icplb_data()
94 bfin_write32(ICPLB_ADDR0 + idx * 4, addr); in write_icplb_data()
264 bfin_write32(regaddr, data); in dcplb_protection_fault()