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Searched refs:div (Results 1 – 25 of 57) sorted by relevance

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/arch/arm/plat-s3c24xx/
Dclock-dclk.c75 unsigned long div; in s3c24xx_calc_div() local
80 div = clk_get_rate(clk->parent) / rate; in s3c24xx_calc_div()
81 if (div < 2) in s3c24xx_calc_div()
82 div = 2; in s3c24xx_calc_div()
83 else if (div > 16) in s3c24xx_calc_div()
84 div = 16; in s3c24xx_calc_div()
86 return div; in s3c24xx_calc_div()
92 unsigned long div = s3c24xx_calc_div(clk, rate); in s3c24xx_round_dclk_rate() local
94 if (div == 0) in s3c24xx_round_dclk_rate()
97 return clk_get_rate(clk->parent) / div; in s3c24xx_round_dclk_rate()
[all …]
/arch/arm/mach-mx1/
Dclock.c65 int div; in _clk_simple_round_rate() local
70 div = parent_rate / rate; in _clk_simple_round_rate()
72 div++; in _clk_simple_round_rate()
74 if (div > limit) in _clk_simple_round_rate()
75 div = limit; in _clk_simple_round_rate()
77 return parent_rate / div; in _clk_simple_round_rate()
245 unsigned int div; in hclk_set_rate() local
251 div = parent_rate / rate; in hclk_set_rate()
253 if (div > 16 || div < 1 || ((parent_rate / div) != rate)) in hclk_set_rate()
256 div--; in hclk_set_rate()
[all …]
/arch/arm/mach-omap2/
Dclock.h46 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
58 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
59 { .div = 0 }
63 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
64 { .div = 0 }
68 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
69 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
70 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
71 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
72 { .div = 0 }
Dclock34xx.h124 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
125 { .div = 0 }
129 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
130 { .div = 0 }
134 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
135 { .div = 0 }
139 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
140 { .div = 0 }
144 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
145 { .div = 0 }
[all …]
Dclock24xx.h731 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
732 { .div = 0 },
736 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
737 { .div = 0 },
770 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
771 { .div = 0 },
775 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
776 { .div = 0 },
804 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
805 { .div = 0 },
[all …]
Dclock.c115 for (clkr = clks->rates; clkr->div && !found; clkr++) { in omap2_init_clksel_parent()
381 u32 div = 0; in omap2_clksel_recalc() local
385 div = omap2_clksel_get_divisor(clk); in omap2_clksel_recalc()
386 if (div == 0) in omap2_clksel_recalc()
389 if (unlikely(clk->rate == clk->parent->rate / div)) in omap2_clksel_recalc()
391 clk->rate = clk->parent->rate / div; in omap2_clksel_recalc()
393 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div); in omap2_clksel_recalc()
461 for (clkr = clks->rates; clkr->div; clkr++) { in omap2_clksel_round_rate_div()
466 if (clkr->div <= last_div) in omap2_clksel_round_rate_div()
470 last_div = clkr->div; in omap2_clksel_round_rate_div()
[all …]
Dgpmc.c182 int div; in gpmc_cs_calc_divider() local
186 div = l / gpmc_get_fclk_period(); in gpmc_cs_calc_divider()
187 if (div > 4) in gpmc_cs_calc_divider()
189 if (div <= 0) in gpmc_cs_calc_divider()
190 div = 1; in gpmc_cs_calc_divider()
192 return div; in gpmc_cs_calc_divider()
197 int div; in gpmc_cs_set_timings() local
200 div = gpmc_cs_calc_divider(cs, t->sync_clk); in gpmc_cs_set_timings()
201 if (div < 0) in gpmc_cs_set_timings()
235 cs, (div * gpmc_get_fclk_period()) / 1000, div); in gpmc_cs_set_timings()
[all …]
Dclock24xx.c103 u32 div = PRCM_CLKSRC_CTRL; in omap2_sys_clk_recalc() local
104 div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ in omap2_sys_clk_recalc()
105 div >>= clk->rate_offset; in omap2_sys_clk_recalc()
106 clk->rate = (clk->parent->rate / div); in omap2_sys_clk_recalc()
194 u32 cur_rate, low, mult, div, valid_rate, done_rate; in omap2_reprogram_dpllcore() local
227 div = ((curr_prcm_set->xtal_speed / 1000000) - 1); in omap2_reprogram_dpllcore()
239 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); in omap2_reprogram_dpllcore()
419 u32 div; in omap2_get_sysclkdiv() local
421 div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); in omap2_get_sysclkdiv()
422 div &= OMAP_SYSCLKDIV_MASK; in omap2_get_sysclkdiv()
[all …]
/arch/arm/mach-s3c2442/
Dclock.c53 int div; in s3c2442_camif_upll_round() local
58 div = parent_rate / rate; in s3c2442_camif_upll_round()
60 if (div == 3) in s3c2442_camif_upll_round()
65 div /= 2; in s3c2442_camif_upll_round()
67 if (div < 1) in s3c2442_camif_upll_round()
68 div = 1; in s3c2442_camif_upll_round()
69 else if (div > 16) in s3c2442_camif_upll_round()
70 div = 16; in s3c2442_camif_upll_round()
72 return parent_rate / (div * 2); in s3c2442_camif_upll_round()
/arch/arm/mach-s3c2443/
Dclock.c112 int div; in s3c2443_roundrate_clksrc() local
119 div = (rate / parent_rate); in s3c2443_roundrate_clksrc()
121 if (div < 1) in s3c2443_roundrate_clksrc()
122 div = 1; in s3c2443_roundrate_clksrc()
123 else if (div > max) in s3c2443_roundrate_clksrc()
124 div = max; in s3c2443_roundrate_clksrc()
126 return parent_rate / div; in s3c2443_roundrate_clksrc()
196 unsigned long div = __raw_readl(S3C2443_CLKDIV0); in s3c2443_getrate_mdivclk() local
198 div &= S3C2443_CLKDIV0_EXTDIV_MASK; in s3c2443_getrate_mdivclk()
199 div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */ in s3c2443_getrate_mdivclk()
[all …]
/arch/arm/mach-rpc/include/mach/
Dacornfb.h85 u_int div; in acornfb_vidc20_find_rates() local
88 div = var->pixclock / 9090; /*9921*/ in acornfb_vidc20_find_rates()
91 if (div == 0) in acornfb_vidc20_find_rates()
92 div = 1; in acornfb_vidc20_find_rates()
93 if (div > 8) in acornfb_vidc20_find_rates()
94 div = 8; in acornfb_vidc20_find_rates()
97 switch (div) { in acornfb_vidc20_find_rates()
136 vidc->pll_ctl = acornfb_vidc20_find_pll(var->pixclock / div); in acornfb_vidc20_find_rates()
/arch/arm/mach-mx3/
Dclock.c34 static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post) in __calc_pre_post_dividers() argument
38 if (div >= 512) { in __calc_pre_post_dividers()
41 } else if (div >= 64) { in __calc_pre_post_dividers()
42 min_pre = (div - 1) / 64 + 1; in __calc_pre_post_dividers()
45 err = div % temp_pre; in __calc_pre_post_dividers()
56 *post = (div + *pre - 1) / *pre; in __calc_pre_post_dividers()
57 } else if (div <= 8) { in __calc_pre_post_dividers()
58 *pre = div; in __calc_pre_post_dividers()
62 *post = div; in __calc_pre_post_dividers()
335 u32 div = parent / rate; in _clk_csi_round_rate() local
[all …]
/arch/arm/mach-s3c2440/
Dclock.c53 int div; in s3c2440_camif_upll_round() local
60 div = (parent_rate / rate) / 2; in s3c2440_camif_upll_round()
62 if (div < 1) in s3c2440_camif_upll_round()
63 div = 1; in s3c2440_camif_upll_round()
64 else if (div > 16) in s3c2440_camif_upll_round()
65 div = 16; in s3c2440_camif_upll_round()
67 return parent_rate / (div * 2); in s3c2440_camif_upll_round()
/arch/sh/kernel/cpu/sh4a/
Dclock-sh7722.c47 unsigned long rem, div; in adjust_pair_of_clocks() local
62 div = r2 / r1; in adjust_pair_of_clocks()
63 pr_debug( "...div = %ld\n", div); in adjust_pair_of_clocks()
73 r2 = r1 * (div + the_one); in adjust_pair_of_clocks()
82 div = r1 / r2; in adjust_pair_of_clocks()
83 pr_debug( "...div = %ld\n", div); in adjust_pair_of_clocks()
93 r2 = r1 / (div + the_one); in adjust_pair_of_clocks()
98 div = r1 / m1; in adjust_pair_of_clocks()
99 r2 = div * m2; in adjust_pair_of_clocks()
100 pr_debug( "...div = %ld\n", div); in adjust_pair_of_clocks()
[all …]
/arch/arm/mach-s3c2412/
Dclock.c163 int div; in s3c2412_roundrate_usbsrc() local
168 div = parent_rate / rate; in s3c2412_roundrate_usbsrc()
169 if (div > 2) in s3c2412_roundrate_usbsrc()
170 div = 2; in s3c2412_roundrate_usbsrc()
172 return parent_rate / div; in s3c2412_roundrate_usbsrc()
178 unsigned long div = __raw_readl(S3C2410_CLKDIVN); in s3c2412_getrate_usbsrc() local
180 return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1); in s3c2412_getrate_usbsrc()
278 int div; in s3c2412_roundrate_clksrc() local
285 div = (rate / parent_rate); in s3c2412_roundrate_clksrc()
287 if (div < 1) in s3c2412_roundrate_clksrc()
[all …]
/arch/arm/mach-mx2/
Dclock_imx27.c266 int div; in _clk_cpu_round_rate() local
271 div = parent_rate / rate; in _clk_cpu_round_rate()
273 div++; in _clk_cpu_round_rate()
275 if (div > 4) in _clk_cpu_round_rate()
276 div = 4; in _clk_cpu_round_rate()
278 return parent_rate / div; in _clk_cpu_round_rate()
283 unsigned int div; in _clk_cpu_set_rate() local
289 div = parent_rate / rate; in _clk_cpu_set_rate()
291 if (div > 4 || div < 1 || ((parent_rate / div) != rate)) in _clk_cpu_set_rate()
294 div--; in _clk_cpu_set_rate()
[all …]
/arch/x86/kernel/cpu/cpufreq/
Dcpufreq-nforce2.c23 #define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div) argument
69 unsigned char mul, div; in nforce2_calc_fsb() local
72 div = pll & 0xff; in nforce2_calc_fsb()
74 if (div > 0) in nforce2_calc_fsb()
75 return NFORCE2_XTAL * mul / div; in nforce2_calc_fsb()
89 unsigned char mul = 0, div = 0; in nforce2_calc_pll() local
93 while (((mul == 0) || (div == 0)) && (tried <= 3)) { in nforce2_calc_pll()
99 div = xdiv; in nforce2_calc_pll()
104 if ((mul == 0) || (div == 0)) in nforce2_calc_pll()
107 return NFORCE2_PLL(mul, div); in nforce2_calc_pll()
/arch/powerpc/boot/
Dcuboot-acadia.c49 unsigned long div; /* total divisor udiv * bdiv */ in get_clocks() local
130 div = plloutb / (16 * baud); /* total divisor */ in get_clocks()
139 ibdiv = div / i; in get_clocks()
141 idiff = (est > div) ? (est-div) : (div-est); in get_clocks()
Dcuboot-52xx.c27 int div; in platform_fixups() local
50 div = in_8(reg + 0x204) & 0x0020 ? 8 : 4; in platform_fixups()
51 sysfreq = bd.bi_busfreq * div; in platform_fixups()
/arch/m68k/atari/
Ddebug.c220 int clksrc, clkmode, div, reg3, reg5; in atari_init_scc_port() local
230 div = div_table[baud]; in atari_init_scc_port()
237 div = 0; in atari_init_scc_port()
254 SCC_WRITE(12, div); /* BRG value */ in atari_init_scc_port()
257 SCC_WRITE(14, brgsrc_table[baud] | (div ? 1 : 0)); in atari_init_scc_port()
270 int div; in atari_init_midi_port() local
277 div = ACIA_DIV64; /* really 7812.5 bps */ in atari_init_midi_port()
279 div = ACIA_DIV1; /* really 500 kbps (does that work??) */ in atari_init_midi_port()
281 div = ACIA_DIV16; /* 31250 bps, standard for MIDI */ in atari_init_midi_port()
284 acia.mid_ctrl = div | csize | parity | in atari_init_midi_port()
/arch/h8300/kernel/timer/
Dtimer8.c85 unsigned int div; in h8300_timer_setup() local
88 calc_param(cnt, div, divide_rate, 0x10000); in h8300_timer_setup()
89 div++; in h8300_timer_setup()
101 ctrl_outw((CMIEA|CCLR_CMA|CKS2) << 8 | div, in h8300_timer_setup()
Dtimer16.c65 unsigned int div; in h8300_timer_setup() local
68 calc_param(cnt, div, divide_rate, 0x10000); in h8300_timer_setup()
74 ctrl_outb(CCLR0 | div, _16BASE + TCR); in h8300_timer_setup()
Ditu.c70 unsigned int div; in h8300_timer_setup() local
73 calc_param(cnt, div, divide_rate, 0x10000); in h8300_timer_setup()
79 ctrl_outb(CCLR0 | div, ITUBASE + TCR); in h8300_timer_setup()
/arch/x86/kernel/acpi/realmode/
Dwakemain.c17 u16 div = 1193181/hz; in beep() local
21 outb(div, 0x42); /* LSB of counter */ in beep()
23 outb(div >> 8, 0x42); /* MSB of counter */ in beep()
/arch/arm/plat-s3c24xx/include/mach/
Dpwm-clock.h50 static inline unsigned long pwm_tdiv_div_bits(unsigned int div) in pwm_tdiv_div_bits() argument
52 return ilog2(div) - 1; in pwm_tdiv_div_bits()

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