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Searched refs:reset_value (Results 1 – 11 of 11) sorted by relevance

/arch/x86/oprofile/
Dop_model_ppro.c44 static u64 *reset_value; variable
71 if (!reset_value) { in ppro_setup_ctrs()
72 reset_value = kmalloc(sizeof(reset_value[0]) * num_counters, in ppro_setup_ctrs()
74 if (!reset_value) in ppro_setup_ctrs()
114 reset_value[i] = counter_config[i].count; in ppro_setup_ctrs()
116 wrmsrl(msrs->counters[i].addr, -reset_value[i]); in ppro_setup_ctrs()
127 reset_value[i] = 0; in ppro_setup_ctrs()
140 if (!reset_value[i]) in ppro_check_ctrs()
145 wrmsrl(msrs->counters[i].addr, -reset_value[i]); in ppro_check_ctrs()
169 if (!reset_value) in ppro_start()
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Dop_model_amd.c50 static unsigned long reset_value[NUM_COUNTERS]; variable
128 reset_value[i] = counter_config[i].count; in op_amd_setup_ctrs()
146 reset_value[i] = 0; in op_amd_setup_ctrs()
232 if (!reset_value[i]) in op_amd_check_ctrs()
237 CTR_WRITE(reset_value[i], msrs, i); in op_amd_check_ctrs()
254 if (reset_value[i]) { in op_amd_start()
290 if (!reset_value[i]) in op_amd_stop()
Dop_model_p4.c394 static unsigned long reset_value[NUM_COUNTERS_NON_HT]; variable
585 reset_value[i] = counter_config[i].count; in p4_setup_ctrs()
589 reset_value[i] = 0; in p4_setup_ctrs()
605 if (!reset_value[i]) in p4_check_ctrs()
631 CTR_WRITE(reset_value[i], real); in p4_check_ctrs()
634 CTR_WRITE(reset_value[i], real); in p4_check_ctrs()
654 if (!reset_value[i]) in p4_start()
671 if (!reset_value[i]) in p4_stop()
/arch/powerpc/oprofile/
Dop_model_pa6t.c40 static u64 reset_value[OP_MAX_COUNTER]; variable
134 reset_value[pmc] = (0x1UL << 39) - ctr[pmc].count; in pa6t_reg_setup()
136 pmc, reset_value[pmc]); in pa6t_reg_setup()
172 ctr_write(i, reset_value[i]); in pa6t_start()
222 ctr_write(i, reset_value[i]); in pa6t_handle_interrupt()
Dop_model_7450.c29 static unsigned long reset_value[OP_MAX_COUNTER]; variable
111 reset_value[i] = 0x80000000UL - ctr[i].count; in fsl7450_reg_setup()
144 classic_ctr_write(i, reset_value[i]); in fsl7450_start()
192 classic_ctr_write(i, reset_value[i]); in fsl7450_handle_interrupt()
Dop_model_rs64.c87 static unsigned long reset_value[OP_MAX_COUNTER]; variable
100 reset_value[i] = 0x80000000UL - ctr[i].count; in rs64_reg_setup()
143 classic_ctr_write(i, reset_value[i]); in rs64_start()
197 classic_ctr_write(i, reset_value[i]); in rs64_handle_interrupt()
Dop_model_power4.c26 static unsigned long reset_value[OP_MAX_COUNTER]; variable
51 reset_value[i] = 0x80000000UL - ctr[i].count; in power4_reg_setup()
130 classic_ctr_write(i, reset_value[i]); in power4_start()
280 classic_ctr_write(i, reset_value[i]); in power4_handle_interrupt()
Dop_model_fsl_emb.c28 static unsigned long reset_value[OP_MAX_COUNTER]; variable
277 reset_value[i] = 0x80000000UL - ctr[i].count; in fsl_emb_reg_setup()
290 ctr_write(i, reset_value[i]); in fsl_emb_start()
349 ctr_write(i, reset_value[i]); in fsl_emb_handle_interrupt()
Dop_model_cell.c184 static u32 reset_value[NR_PHYS_CTRS]; variable
748 reset_value[0] = 0xFFFFFFFF - ctr[0].count; in cell_reg_setup_spu_events()
755 spu_pm_cnt[i] = reset_value[0]; in cell_reg_setup_spu_events()
823 reset_value[i] = 0xFFFFFFFF - ctr[i].count; in cell_reg_setup_ppu()
836 per_cpu(pmc_values, cpu)[i] = reset_value[i]; in cell_reg_setup_ppu()
1376 cbe_write_ctr(cpu, 0, reset_value[0]); in cell_global_start_spu_events()
1422 cbe_write_ctr(cpu, i, reset_value[i]); in cell_global_start_ppu()
1529 cbe_write_ctr(cpu, 0, reset_value[0]); in cell_handle_interrupt_spu()
1651 cbe_write_ctr(cpu, i, reset_value[i]); in cell_handle_interrupt_ppu()
/arch/x86/include/asm/
Dds.h205 unsigned long long reset_value; member
/arch/x86/kernel/
Dds.c850 tracer->trace.reset_value = in ds_read_pebs()